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gpu: nvgpu: perf: fix MISRA 10.3 violations

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Fix MISRA Rule 10.3 violations in common/pmu/perf for assigning objects
of different size or essential type.

JIRA NVGPU-1008

Change-Id: I7fa7f981ba80c2d6951821ed3c847a814fc8b3b6
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2027654
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Philip Elcan
2019-02-13 11:21:41 -05:00
committed by mobile promotions
parent 967f6defd0
commit bfc3c57afb
3 changed files with 7 additions and 7 deletions
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6
drivers/gpu/nvgpu/common/pmu/perf/perf_gv100.c
View File

@@ -82,11 +82,11 @@ static int gv100_pmu_handle_perf_event(struct gk20a *g, void *pmumsg)
return 0;
}
static u32 perf_pmu_init_vfe_perf_event(struct gk20a *g)
static int perf_pmu_init_vfe_perf_event(struct gk20a *g)
{
struct perf_pmupstate *perf_pmu = g->perf_pmu;
char thread_name[64];
u32 err = 0;
int err = 0;
nvgpu_log_fn(g, " ");
@@ -97,7 +97,7 @@ static u32 perf_pmu_init_vfe_perf_event(struct gk20a *g)
err = nvgpu_thread_create(&perf_pmu->vfe_init.state_task, g,
pmu_set_boot_clk_runcb_fn, thread_name);
if (err != 0U) {
if (err != 0) {
nvgpu_err(g, "failed to start nvgpu_vfe_invalidate_init thread");
}

4
drivers/gpu/nvgpu/common/pmu/perf/vfe_var.c
View File

@@ -1188,9 +1188,9 @@ static int devinit_get_vfe_var_table(struct gk20a *g,
var.param1;
if (szfmt >= VBIOS_VFE_3X_VAR_ENTRY_SIZE_19) {
var_data.single_sensed_fuse.vfield_info.hw_correction_scale =
(int)var.param2;
var.param2;
var_data.single_sensed_fuse.vfield_info.hw_correction_offset =
var.param3;
(int)var.param3;
} else {
var_data.single_sensed_fuse.vfield_info.hw_correction_scale =
BIT32(12);

4
drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperf.h
View File

@@ -88,7 +88,7 @@ struct nv_pmu_perf_cmd_rpc {
};
#define NV_PMU_PERF_CMD_RPC_ALLOC_OFFSET \
offsetof(struct nv_pmu_perf_cmd_rpc, request)
(u32)offsetof(struct nv_pmu_perf_cmd_rpc, request)
/*!
* Simply a union of all specific PERF commands. Forms the general packet
@@ -137,7 +137,7 @@ struct nv_pmu_perf_msg_rpc {
};
#define NV_PMU_PERF_MSG_RPC_ALLOC_OFFSET \
(offsetof(struct nv_pmu_perf_msg_rpc, response))
((u32)offsetof(struct nv_pmu_perf_msg_rpc, response))
/*!
* Simply a union of all specific PERF messages. Forms the general packet