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65a362c01a
clk_vin data structures updated as new calibration type (v20) is added. GP106 header does not have vin calibration type. Assuming V10 if calibration type is not V20. Add fuse calibration for V20 type. Bug 200399373 Change-Id: I9449de1ecb0d0873f3bc16f46660f93fab5b9eac Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1687591 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
111 lines
4.3 KiB
C
111 lines
4.3 KiB
C
/*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _ctrlclkavfs_h_
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#define _ctrlclkavfs_h_
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#include "ctrlboardobj.h"
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/*!
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* Valid global VIN ID values
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*/
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#define CTRL_CLK_VIN_ID_SYS 0x00000000
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#define CTRL_CLK_VIN_ID_LTC 0x00000001
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#define CTRL_CLK_VIN_ID_XBAR 0x00000002
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#define CTRL_CLK_VIN_ID_GPC0 0x00000003
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#define CTRL_CLK_VIN_ID_GPC1 0x00000004
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#define CTRL_CLK_VIN_ID_GPC2 0x00000005
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#define CTRL_CLK_VIN_ID_GPC3 0x00000006
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#define CTRL_CLK_VIN_ID_GPC4 0x00000007
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#define CTRL_CLK_VIN_ID_GPC5 0x00000008
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#define CTRL_CLK_VIN_ID_GPCS 0x00000009
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#define CTRL_CLK_VIN_ID_SRAM 0x0000000A
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#define CTRL_CLK_VIN_ID_UNDEFINED 0x000000FF
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#define CTRL_CLK_VIN_TYPE_DISABLED 0x00000000
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#define CTRL_CLK_VIN_TYPE_V10 0x00000001
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#define CTRL_CLK_VIN_TYPE_V20 0x00000002
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/*!
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* Various types of VIN calibration that the GPU can support
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*/
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#define CTRL_CLK_VIN_CAL_TYPE_V10 (0x00000000)
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#define CTRL_CLK_VIN_CAL_TYPE_V20 (0x00000001)
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/*!
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* Mask of all GPC VIN IDs supported by RM
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*/
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#define CTRL_CLK_VIN_MASK_UNICAST_GPC (BIT(CTRL_CLK_VIN_ID_GPC0) | \
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BIT(CTRL_CLK_VIN_ID_GPC1) | \
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BIT(CTRL_CLK_VIN_ID_GPC2) | \
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BIT(CTRL_CLK_VIN_ID_GPC3) | \
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BIT(CTRL_CLK_VIN_ID_GPC4) | \
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BIT(CTRL_CLK_VIN_ID_GPC5))
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#define CTRL_CLK_LUT_NUM_ENTRIES 0x50
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#define CTRL_CLK_VIN_STEP_SIZE_UV (10000)
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#define CTRL_CLK_LUT_MIN_VOLTAGE_UV (450000)
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#define CTRL_CLK_FLL_TYPE_DISABLED 0
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#define CTRL_CLK_FLL_ID_SYS (0x00000000)
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#define CTRL_CLK_FLL_ID_LTC (0x00000001)
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#define CTRL_CLK_FLL_ID_XBAR (0x00000002)
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#define CTRL_CLK_FLL_ID_GPC0 (0x00000003)
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#define CTRL_CLK_FLL_ID_GPC1 (0x00000004)
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#define CTRL_CLK_FLL_ID_GPC2 (0x00000005)
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#define CTRL_CLK_FLL_ID_GPC3 (0x00000006)
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#define CTRL_CLK_FLL_ID_GPC4 (0x00000007)
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#define CTRL_CLK_FLL_ID_GPC5 (0x00000008)
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#define CTRL_CLK_FLL_ID_GPCS (0x00000009)
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#define CTRL_CLK_FLL_ID_UNDEFINED (0x000000FF)
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#define CTRL_CLK_FLL_MASK_UNDEFINED (0x00000000)
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/*!
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* Mask of all GPC FLL IDs supported by RM
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*/
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#define CTRL_CLK_FLL_MASK_UNICAST_GPC (BIT(CTRL_CLK_FLL_ID_GPC0) | \
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BIT(CTRL_CLK_FLL_ID_GPC1) | \
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BIT(CTRL_CLK_FLL_ID_GPC2) | \
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BIT(CTRL_CLK_FLL_ID_GPC3) | \
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BIT(CTRL_CLK_FLL_ID_GPC4) | \
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BIT(CTRL_CLK_FLL_ID_GPC5))
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/*!
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* Mask of all FLL IDs supported by Nvgpu driver
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*/
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#define CTRL_CLK_FLL_ID_ALL_MASK (BIT(CTRL_CLK_FLL_ID_SYS) | \
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BIT(CTRL_CLK_FLL_ID_LTC) | \
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BIT(CTRL_CLK_FLL_ID_XBAR) | \
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BIT(CTRL_CLK_FLL_ID_GPC0) | \
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BIT(CTRL_CLK_FLL_ID_GPC1) | \
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BIT(CTRL_CLK_FLL_ID_GPC2) | \
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BIT(CTRL_CLK_FLL_ID_GPC3) | \
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BIT(CTRL_CLK_FLL_ID_GPC4) | \
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BIT(CTRL_CLK_FLL_ID_GPC5) | \
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BIT(CTRL_CLK_FLL_ID_GPCS))
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#define CTRL_CLK_FLL_REGIME_ID_INVALID (0x00000000)
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#define CTRL_CLK_FLL_REGIME_ID_FFR (0x00000001)
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#define CTRL_CLK_FLL_REGIME_ID_FR (0x00000002)
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#define CTRL_CLK_FLL_LUT_VSELECT_LOGIC (0x00000000)
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#define CTRL_CLK_FLL_LUT_VSELECT_MIN (0x00000001)
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#define CTRL_CLK_FLL_LUT_VSELECT_SRAM (0x00000002)
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#endif
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