Tejal Kudav b269aae9f2 gpu: nvgpu: correct usage of pbdma_id ...

The pbdma_id field stored in struct nvgpu_device is bitmask and not
bit position as implied by the name. This field is incorrectly used as
bit position in nvgpu_engine_disable_activity(), causing PRI timeout
errors during iGPU and dGPU shutdown path.

PRI timeout errors-
nvgpu: 17000000.gv11b                  gk20a_ptimer_isr:54   [ERR]
PRI timeout: ADR 0x0000308c READ  DATA 0x00000000

Here the pbdma_id stored in struct nvgpu_device for runlist_0 on
gv11b is 0x3(bitmask corresponding to PBDMA_0 and PBDMA_1).
nvgpu_engine_disable_activity() interprets this as PBDMA_3 and adds
incorrect offset to access PBDMA_STATUS register, causing PRI error.

Modify nvgpu_engine_disable_activity() to treat pbdma_id as bitmask
and loop through set bits.

JIRA NVGPU-5991

Change-Id: Iaffb974cddaa375a329e70f3b5903b9ef2a222c4
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2397954
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>

2020-12-15 14:13:28 -06:00

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