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b49903b51c8cbda42eebd733d83b8cc1e9349700
linux-nvgpu/drivers/gpu/nvgpu/gk20a
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Terje Bergstrom f6927096e9 gpu: nvgpu: Add HAL for add ZBC color & depth 
Turn add ZBC functions into HALs that can be filled per chip.

Bug 1567274

Change-Id: Ic6ef29d3353d4a0079ea0c80f513ffd579fe554f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/601109
Reviewed-by: Automatic_Commit_Validation_User
2015-03-18 12:12:17 -07:00
..
as_gk20a.c
gpu: nvgpu: Implement NVGPU_AS_IOCTL_GET_VA_REGIONS
2015-03-18 12:12:08 -07:00
as_gk20a.h
gpu: nvgpu: Implement 64k large page support
2015-03-18 12:11:46 -07:00
cde_gk20a.c
gpu: nvgpu: cde: wait for ctx deletion before get
2015-03-18 12:12:16 -07:00
cde_gk20a.h
gpu: nvgpu: cde: combine init and convert passes
2015-03-18 12:12:16 -07:00
channel_gk20a.c
gpu: nvgpu: add trace event for channel update
2015-03-18 12:12:14 -07:00
channel_gk20a.h
gpu: nvgpu: protect channel update callback access
2015-03-18 12:11:58 -07:00
channel_sync_gk20a.c
gpu: nvgpu: fix sparse warnings
2015-03-18 12:12:01 -07:00
channel_sync_gk20a.h
gpu: nvgpu: Add gk20a_fence type
2015-03-18 12:10:40 -07:00
clk_gk20a.c
arm: tegra: Register tegra-throttle cdev as driver
2015-03-18 12:10:43 -07:00
clk_gk20a.h
gpu: nvgpu: Fix build without Tegra clk framework
2015-03-18 12:11:50 -07:00
ctrl_gk20a.c
gpu: nvgpu: GPU characteristics additions
2015-03-18 12:12:07 -07:00
ctrl_gk20a.h
gpu: nvgpu: rename gpu ioctls and structs to nvgpu
2015-03-18 12:11:33 -07:00
dbg_gpu_gk20a.c
gpu: nvgpu: fix sparse warnings
2015-03-18 12:12:01 -07:00
dbg_gpu_gk20a.h
gpu: nvgpu: rename gpu ioctls and structs to nvgpu
2015-03-18 12:11:33 -07:00
debug_gk20a.c
gpu: nvgpu: Add NULL pointer check to debug code
2015-03-18 12:12:10 -07:00
debug_gk20a.h
gpu: nvgpu: rename gpu ioctls and structs to nvgpu
2015-03-18 12:11:33 -07:00
fb_gk20a.c
gpu: nvgpu: Implement 64k large page support
2015-03-18 12:11:46 -07:00
fb_gk20a.h
gpu: nvgpu: rename gpu ioctls and structs to nvgpu
2015-03-18 12:11:33 -07:00
fence_gk20a.c
gpu: nvgpu: Use long for timeout in semaphores
2015-03-18 12:12:12 -07:00
fence_gk20a.h
gpu: nvgpu: Add gk20a_fence type
2015-03-18 12:10:40 -07:00
fifo_gk20a.c
gpu: nvgpu: Retrieve intr & reset id from HW
2015-03-18 12:12:14 -07:00
fifo_gk20a.h
gpu: nvgpu: Retrieve intr & reset id from HW
2015-03-18 12:12:14 -07:00
gk20a_allocator.c
gpu: nvgpu: Per-alloc alignment
2015-03-18 12:12:15 -07:00
gk20a_allocator.h
gpu: nvgpu: Per-alloc alignment
2015-03-18 12:12:15 -07:00
gk20a_gating_reglist.c
gpu: nvgpu: fix sparse warnings
2015-03-18 12:12:01 -07:00
gk20a_gating_reglist.h
gpu: nvgpu: gm20b: Regenerate clock gating lists
2015-03-18 12:11:09 -07:00
gk20a_scale.c
gpu: nvgpu: Add sw shadow for load value
2015-03-18 12:10:45 -07:00
gk20a_scale.h
gpu: nvgpu: Fix build without Tegra clk framework
2015-03-18 12:11:50 -07:00
gk20a_sysfs.c
gpu: nvgpu: support config of TPC FUSE dynamically
2015-03-18 12:12:10 -07:00
gk20a.c
gpu: nvgpu: Retrieve intr & reset id from HW
2015-03-18 12:12:14 -07:00
gk20a.h
gpu: nvgpu: Add HAL for add ZBC color & depth
2015-03-18 12:12:17 -07:00
gr_ctx_gk20a_sim.c
gpu: nvgpu: Add NVIDIA GPU Driver
2015-03-18 12:08:53 -07:00
gr_ctx_gk20a.c
gpu: nvgpu: fix sparse warnings
2015-03-18 12:12:01 -07:00
gr_ctx_gk20a.h
video: tegra: host: flexible to select fw per chip
2015-03-18 12:08:54 -07:00
gr_gk20a.c
gpu: nvgpu: Add HAL for add ZBC color & depth
2015-03-18 12:12:17 -07:00
gr_gk20a.h
gpu: nvgpu: Add HAL for add ZBC color & depth
2015-03-18 12:12:17 -07:00
gr_pri_gk20a.h
gpu: nvgpu: gm20b: halify tpc lookup
2015-03-18 12:11:57 -07:00
hal_gk20a.c
gpu: nvgpu: Add class numbers to characteristics
2015-03-18 12:12:06 -07:00
hal_gk20a.h
gpu: nvgpu: Add class numbers to characteristics
2015-03-18 12:12:06 -07:00
hal.c
gpu: nvgpu: Add class numbers to characteristics
2015-03-18 12:12:06 -07:00
hal.h
gpu: nvgpu: Add NVIDIA GPU Driver
2015-03-18 12:08:53 -07:00
hw_bus_gk20a.h
gpu: nvgpu: Add NVIDIA GPU Driver
2015-03-18 12:08:53 -07:00
hw_ccsr_gk20a.h
gpu: nvgpu: Add NVIDIA GPU Driver
2015-03-18 12:08:53 -07:00
hw_ctxsw_prog_gk20a.h
gpu: sysfs mode for allowing access to registers
2015-03-18 12:10:49 -07:00
hw_fb_gk20a.h
gpu: nvgpu: Sync gk20a and gm20b headers
2015-03-18 12:11:52 -07:00
hw_fifo_gk20a.h
gpu: nvgpu: Sync gk20a and gm20b headers
2015-03-18 12:11:52 -07:00
hw_flush_gk20a.h
gpu: nvgpu: Add NVIDIA GPU Driver
2015-03-18 12:08:53 -07:00
hw_gmmu_gk20a.h
gpu: nvgpu: Sync gk20a and gm20b headers
2015-03-18 12:11:52 -07:00
hw_gr_gk20a.h
gpu: nvgpu: GPU characteristics additions
2015-03-18 12:12:07 -07:00
hw_ltc_gk20a.h
gpu: nvgpu: Sync gk20a and gm20b headers
2015-03-18 12:11:52 -07:00
hw_mc_gk20a.h
gpu: nvgpu: gk20a, gm20b headers
2015-03-18 12:09:42 -07:00
hw_pbdma_gk20a.h
gpu: nvgpu: Increase PBDMA timeout
2015-03-18 12:10:52 -07:00
hw_pri_ringmaster_gk20a.h
gpu: nvgpu: Add NVIDIA GPU Driver
2015-03-18 12:08:53 -07:00
hw_pri_ringstation_fbp_gk20a.h
gpu: nvgpu: Add NVIDIA GPU Driver
2015-03-18 12:08:53 -07:00
hw_pri_ringstation_gpc_gk20a.h
gpu: nvgpu: Add NVIDIA GPU Driver
2015-03-18 12:08:53 -07:00
hw_pri_ringstation_sys_gk20a.h
gpu: nvgpu: Add NVIDIA GPU Driver
2015-03-18 12:08:53 -07:00
hw_proj_gk20a.h
gpu: nvgpu: Add NVIDIA GPU Driver
2015-03-18 12:08:53 -07:00
hw_pwr_gk20a.h
gpu: nvgpu: Sync gk20a and gm20b headers
2015-03-18 12:11:52 -07:00
hw_ram_gk20a.h
gpu: nvgpu: Sync gk20a and gm20b headers
2015-03-18 12:11:52 -07:00
hw_sim_gk20a.h
gpu: nvgpu: Add NVIDIA GPU Driver
2015-03-18 12:08:53 -07:00
hw_therm_gk20a.h
gpu: nvgpu: Sync gk20a and gm20b headers
2015-03-18 12:11:52 -07:00
hw_timer_gk20a.h
gpu: nvgpu: Add NVIDIA GPU Driver
2015-03-18 12:08:53 -07:00
hw_top_gk20a.h
gpu: nvgpu: Retrieve intr & reset id from HW
2015-03-18 12:12:14 -07:00
hw_trim_gk20a.h
gpu: nvgpu: Sync gk20a and gm20b headers
2015-03-18 12:11:52 -07:00
kind_gk20a.c
gpu: nvgpu: Use noinline_for_stack to avoid GCOV build break
2015-03-18 12:10:41 -07:00
kind_gk20a.h
gpu: nvgpu: Add NVIDIA GPU Driver
2015-03-18 12:08:53 -07:00
ltc_common.c
Revert "gpu: nvgpu: GR and LTC HAL to use const structs"
2015-03-18 12:11:56 -07:00
ltc_gk20a.c
gpu: nvgpu: Per-alloc alignment
2015-03-18 12:12:15 -07:00
ltc_gk20a.h
gpu: nvgpu: Add class numbers to characteristics
2015-03-18 12:12:06 -07:00
mc_gk20a.c
gpu: nvgpu: Retrieve intr & reset id from HW
2015-03-18 12:12:14 -07:00
mc_gk20a.h
gpu: nvgpu: Per-chip interrupt processing
2015-03-18 12:11:56 -07:00
mm_gk20a.c
gpu: nvgpu: l2 invalidate/flush for off devices
2015-03-18 12:12:17 -07:00
mm_gk20a.h
gpu: nvgpu: cde: Combine H and V passes
2015-03-18 12:12:06 -07:00
platform_gk20a_generic.c
gpu: nvgpu: Enable clocks only if defined
2015-03-18 12:11:51 -07:00
platform_gk20a_tegra.c
nvgpu: gm20b: set rail gating delay to 500msec
2015-03-18 12:12:12 -07:00
platform_gk20a.h
gpu: nvgpu: force CAR reset in do_idle() for gm20b
2015-03-18 12:12:04 -07:00
platform_vgpu_tegra.c
gpu: nvgpu: vgpu: init vm->gmmu_page_sizes
2015-03-18 12:11:59 -07:00
pmu_gk20a.c
gpu: nvgpu: Per-alloc alignment
2015-03-18 12:12:15 -07:00
pmu_gk20a.h
gpu: nvgpu: Changes to support LS sig
2015-03-18 12:11:56 -07:00
priv_ring_gk20a.c
gpu: nvgpu: gm20b: Regenerate clock gating lists
2015-03-18 12:11:09 -07:00
priv_ring_gk20a.h
gpu: nvgpu: Add NVIDIA GPU Driver
2015-03-18 12:08:53 -07:00
regops_gk20a.c
gpu: nvgpu: fix sparse warnings
2015-03-18 12:12:01 -07:00
regops_gk20a.h
gpu: nvgpu: create new nvgpu ioctl header
2015-03-18 12:11:33 -07:00
semaphore_gk20a.c
gpu: nvgpu: Per-alloc alignment
2015-03-18 12:12:15 -07:00
semaphore_gk20a.h
gpu: nvgpu: rename gpu ioctls and structs to nvgpu
2015-03-18 12:11:33 -07:00
sim_gk20a.h
gpu: nvgpu: Add NVIDIA GPU Driver
2015-03-18 12:08:53 -07:00
sync_gk20a.c
gpu: nvgpu: gk20a: Fix non static symbol
2015-03-18 12:11:46 -07:00
sync_gk20a.h
gpu: nvgpu: Add gk20a_fence type
2015-03-18 12:10:40 -07:00
therm_gk20a.c
gpu: nvgpu: Sync gk20a and gm20b headers
2015-03-18 12:11:52 -07:00
therm_gk20a.h
gpu: nvgpu: rename gpu ioctls and structs to nvgpu
2015-03-18 12:11:33 -07:00
tsg_gk20a.c
gpu: nvgpu: Add ioctl to create new TSG
2015-03-18 12:11:50 -07:00
tsg_gk20a.h
gpu: nvgpu: Add ioctl to create new TSG
2015-03-18 12:11:50 -07:00