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0bf1e8773b
MISRA Rule 10.3 prohibits implicit assignment to different essential or narrower types. This fixes a number of MISRA 10.3 violations in common/boardobj. JIRA NVGPU-2956 Change-Id: I3ad2376b5f61607693b3c553dce09d6ced429374 Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2077495 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Scott Long <scottl@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
102 lines
2.8 KiB
C
102 lines
2.8 KiB
C
/*
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* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/kmem.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/boardobj.h>
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#include <nvgpu/pmuif/ctrlboardobj.h>
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int boardobj_construct_super(struct gk20a *g, struct boardobj **ppboardobj,
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size_t size, void *args)
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{
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struct boardobj *pboardobj = NULL;
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struct boardobj *devtmp = (struct boardobj *)args;
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nvgpu_log_info(g, " ");
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if (devtmp == NULL) {
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return -EINVAL;
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}
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if (*ppboardobj == NULL) {
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*ppboardobj = nvgpu_kzalloc(g, size);
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if (*ppboardobj == NULL) {
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return -ENOMEM;
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}
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(*ppboardobj)->allocated = true;
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}
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pboardobj = *ppboardobj;
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pboardobj->g = g;
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pboardobj->type = devtmp->type;
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pboardobj->idx = CTRL_BOARDOBJ_IDX_INVALID;
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pboardobj->type_mask = BIT32(pboardobj->type) | devtmp->type_mask;
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pboardobj->implements = boardobj_implements_super;
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pboardobj->destruct = boardobj_destruct_super;
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pboardobj->pmudatainit = boardobj_pmudatainit_super;
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nvgpu_list_add(&pboardobj->node, &g->boardobj_head);
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return 0;
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}
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int boardobj_destruct_super(struct boardobj *pboardobj)
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{
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struct gk20a *g = pboardobj->g;
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nvgpu_log_info(g, " ");
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if (pboardobj == NULL) {
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return -EINVAL;
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}
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nvgpu_list_del(&pboardobj->node);
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if (pboardobj->allocated) {
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nvgpu_kfree(pboardobj->g, pboardobj);
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}
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return 0;
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}
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bool boardobj_implements_super(struct gk20a *g, struct boardobj *pboardobj,
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u8 type)
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{
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nvgpu_log_info(g, " ");
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return (0U != (pboardobj->type_mask & BIT(type)));
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}
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int boardobj_pmudatainit_super(struct gk20a *g, struct boardobj *pboardobj,
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struct nv_pmu_boardobj *pmudata)
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{
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nvgpu_log_info(g, " ");
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if (pboardobj == NULL) {
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return -EINVAL;
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}
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if (pmudata == NULL) {
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return -EINVAL;
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}
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pmudata->type = pboardobj->type;
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nvgpu_log_info(g, " Done");
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return 0;
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}
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