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gpu: nvgpu: boardobj: fix MISRA 10.3 issues

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MISRA Rule 10.3 prohibits implicit assignment to different essential or
narrower types. This fixes a number of MISRA 10.3 violations in
common/boardobj.

JIRA NVGPU-2956

Change-Id: I3ad2376b5f61607693b3c553dce09d6ced429374
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077495
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Scott Long <scottl@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Philip Elcan
2019-03-18 16:25:22 -04:00
committed by mobile promotions
parent e2fe43fd42
commit 0bf1e8773b
3 changed files with 10 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/common/boardobj/boardobj.c
View File

@@ -49,7 +49,7 @@ int boardobj_construct_super(struct gk20a *g, struct boardobj **ppboardobj,
pboardobj->g = g;
pboardobj->type = devtmp->type;
pboardobj->idx = CTRL_BOARDOBJ_IDX_INVALID;
pboardobj->type_mask = BIT(pboardobj->type) | devtmp->type_mask;
pboardobj->type_mask = BIT32(pboardobj->type) | devtmp->type_mask;
pboardobj->implements = boardobj_implements_super;
pboardobj->destruct = boardobj_destruct_super;

9
drivers/gpu/nvgpu/common/boardobj/boardobjgrp.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -970,6 +970,7 @@ static int boardobjgrp_pmucmdsend(struct gk20a *g,
struct pmu_cmd cmd;
u32 seqdesc;
int status = 0;
size_t tmp_size;
nvgpu_log_info(g, " ");
@@ -977,8 +978,10 @@ static int boardobjgrp_pmucmdsend(struct gk20a *g,
(void) memset(&handlerparams, 0, sizeof(handlerparams));
(void) memset(&cmd, 0, sizeof(struct pmu_cmd));
cmd.hdr.unit_id = pboardobjgrp->pmu.unitid;
cmd.hdr.size = sizeof(struct nv_pmu_boardobj_cmd_grp) +
tmp_size = sizeof(struct nv_pmu_boardobj_cmd_grp) +
sizeof(struct pmu_hdr);
nvgpu_assert(tmp_size <= (size_t)U8_MAX);
cmd.hdr.size = U8(tmp_size);
pgrpcmd = &cmd.cmd.boardobj.grp;
pgrpcmd->cmd_type = pcmd->id;
@@ -998,7 +1001,7 @@ static int boardobjgrp_pmucmdsend(struct gk20a *g,
* but PMU access pmu boardobjgrp data from vidmem copied above
*/
payload.in.buf = pcmd->buf;
payload.in.size = max(pcmd->hdrsize, pcmd->entrysize);
payload.in.size = U32(max(pcmd->hdrsize, pcmd->entrysize));
payload.in.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
payload.in.offset = offsetof(struct nv_pmu_boardobj_cmd_grp, grp);

6
drivers/gpu/nvgpu/common/boardobj/boardobjgrpmask.c
View File

@@ -236,7 +236,7 @@ int boardobjgrpmask_bitclr(struct boardobjgrpmask *mask, u8 bitidx)
index = CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX(bitidx);
offset = CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_OFFSET(bitidx);
mask->data[index] &= ~BIT(offset);
mask->data[index] &= ~BIT32(offset);
return 0;
}
@@ -256,7 +256,7 @@ int boardobjgrpmask_bitset(struct boardobjgrpmask *mask, u8 bitidx)
index = CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX(bitidx);
offset = CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_OFFSET(bitidx);
mask->data[index] |= BIT(offset);
mask->data[index] |= BIT32(offset);
return 0;
}
@@ -276,7 +276,7 @@ int boardobjgrpmask_bitinv(struct boardobjgrpmask *mask, u8 bitidx)
index = CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX(bitidx);
offset = CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_OFFSET(bitidx);
mask->data[index] ^= ~BIT(offset);
mask->data[index] ^= ~BIT32(offset);
return 0;
}