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5af8cedf05
Enable logging and error reporting for MIF, DLPL, and TLC blocks. Configure the NVLIPT and IOCTRL interrupt registers to rollup the MIF and TLC errors on the link-specific fatal line and the DLPL interrupts on link-specific intr_a(fatal) line. Both link_err_fatal and link_intr_a are rolled up to stall interrupt line. In the handling ISR, clear the interrupt status registers and print an error. Move the interrupt handling HAL code to /common/hal. JIRA NVGPU-4350 JIRA NVGPU-4351 JIRA NVGPU-5231 JIRA NVGPU-4354 JIRA NVGPU-4355 JIRA NVGPU-4356 Change-Id: I14812499caf506592f3ae84d6681d857730d31ff Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2313221 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
89 lines
2.0 KiB
C
89 lines
2.0 KiB
C
/*
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* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/nvlink.h>
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#include <nvgpu/bug.h>
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#include <nvgpu/nvlink_probe.h>
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struct gk20a;
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struct nvgpu_firmware;
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int nvgpu_nvlink_enumerate(struct gk20a *g)
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{
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return -ENOSYS;
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}
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int nvgpu_nvlink_register_device(struct gk20a *g)
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{
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BUG();
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return 0;
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}
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int nvgpu_nvlink_unregister_device(struct gk20a *g)
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{
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BUG();
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return 0;
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}
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int nvgpu_nvlink_register_link(struct gk20a *g)
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{
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BUG();
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return 0;
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}
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int nvgpu_nvlink_unregister_link(struct gk20a *g)
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{
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BUG();
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return 0;
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}
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int nvgpu_nvlink_setup_ndev(struct gk20a *g)
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{
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BUG();
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return 0;
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}
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int nvgpu_nvlink_init_ops(struct gk20a *g)
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{
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BUG();
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return 0;
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}
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int nvgpu_nvlink_read_dt_props(struct gk20a *g)
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{
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BUG();
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return 0;
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}
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int nvgpu_nvlink_minion_load_ucode(struct gk20a *g,
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struct nvgpu_firmware *nvgpu_minion_fw)
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{
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BUG();
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return 0;
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}
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void nvgpu_nvlink_free_minion_used_mem(struct gk20a *g,
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struct nvgpu_firmware *nvgpu_minion_fw)
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{
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BUG();
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}
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