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be5312cb9b
- Define falcon ID for OFA and NVJPG - Initialize falcon sw for OFA and NVJPG - Program boot_vector before riscv kick-start Jira NVGPU-9429 Bug 3962979 Change-Id: If6e63cb1e99ada3742b708bb0f8f7edc64366318 Signed-off-by: Santosh BS <santoshb@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2913882 Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
46 lines
2.2 KiB
C
46 lines
2.2 KiB
C
/*
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* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_FALCON_GA10B_H
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#define NVGPU_FALCON_GA10B_H
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#include <nvgpu/falcon.h>
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#define FALCON_DMEM_BLKSIZE2 8U
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u32 ga10b_falcon_dmemc_blk_mask(void);
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u32 ga10b_falcon_imemc_blk_field(u32 blk);
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u32 ga10b_falcon_get_mem_size(struct nvgpu_falcon *flcn,
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enum falcon_mem_type mem_type);
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bool ga10b_falcon_is_cpu_halted(struct nvgpu_falcon *flcn);
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void ga10b_falcon_set_bcr(struct nvgpu_falcon *flcn);
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void ga10b_falcon_bootstrap(struct nvgpu_falcon *flcn, u64 boot_vector);
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void ga10b_falcon_dump_brom_stats(struct nvgpu_falcon *flcn);
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u32 ga10b_falcon_get_brom_retcode(struct nvgpu_falcon *flcn);
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bool ga10b_falcon_is_priv_lockdown(struct nvgpu_falcon *flcn);
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bool ga10b_falcon_check_brom_passed(u32 retcode);
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bool ga10b_falcon_check_brom_failed(u32 retcode);
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void ga10b_falcon_brom_config(struct nvgpu_falcon *flcn, u64 fmc_code_addr,
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u64 fmc_data_addr, u64 manifest_addr);
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void ga10b_falcon_dump_stats(struct nvgpu_falcon *flcn);
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bool ga10b_is_falcon_scrubbing_done(struct nvgpu_falcon *flcn);
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bool ga10b_is_falcon_idle(struct nvgpu_falcon *flcn);
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#endif /* NVGPU_FALCON_GA10B_H */
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