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gpu: nvgpu: falcon2/riscv update for multimedia

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- Define falcon ID for OFA and NVJPG
- Initialize falcon sw for OFA and NVJPG
- Program boot_vector before riscv kick-start

Jira NVGPU-9429
Bug 3962979

Change-Id: If6e63cb1e99ada3742b708bb0f8f7edc64366318
Signed-off-by: Santosh BS <santoshb@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2913882
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Santosh BS
2023-06-01 07:17:22 +00:00
committed by mobile promotions
parent 912cb15999
commit be5312cb9b
11 changed files with 74 additions and 31 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
drivers/gpu/nvgpu/common/falcon/falcon.c
View File

@@ -472,13 +472,19 @@ struct nvgpu_falcon *nvgpu_falcon_get_instance(struct gk20a *g, u32 flcn_id)
case FALCON_ID_GSPLITE:
flcn = &g->gsp_flcn;
break;
#ifdef CONFIG_NVGPU_DGPU
case FALCON_ID_NVDEC:
flcn = &g->nvdec_flcn;
break;
case FALCON_ID_NVENC:
flcn = &g->nvenc_flcn;
break;
case FALCON_ID_OFA:
flcn = &g->ofa_flcn;
break;
case FALCON_ID_NVDEC:
flcn = &g->nvdec_flcn;
break;
case FALCON_ID_NVJPG:
flcn = &g->nvjpg_flcn;
break;
#ifdef CONFIG_NVGPU_DGPU
case FALCON_ID_SEC2:
flcn = &g->sec2.flcn;
break;
@@ -869,7 +875,6 @@ void nvgpu_falcon_get_ctls(struct nvgpu_falcon *flcn, u32 *sctl, u32 *cpuctl)
s32 nvgpu_falcon_load_ucode(struct nvgpu_falcon *flcn,
struct nvgpu_mem *ucode_mem_desc, u32 *ucode_header)
{
s32 status = -EINVAL;
struct gk20a *g;
if (!is_falcon_valid(flcn)) {
@@ -880,12 +885,9 @@ s32 nvgpu_falcon_load_ucode(struct nvgpu_falcon *flcn,
if (g->ops.falcon.load_ucode == NULL) {
nvgpu_err(g, "hal for loading ucode not set");
goto exit;
return -EINVAL;
}
/* Load ucode */
status = g->ops.falcon.load_ucode(flcn, ucode_mem_desc, ucode_header);
exit:
return status;
return g->ops.falcon.load_ucode(flcn, ucode_mem_desc, ucode_header);
}

28
drivers/gpu/nvgpu/common/init/nvgpu_init.c
View File

@@ -259,6 +259,7 @@ static int nvgpu_falcons_sw_init(struct gk20a *g)
nvgpu_err(g, "failed to sw init FALCON_ID_SEC2");
goto done_fecs;
}
#endif
err = g->ops.falcon.falcon_sw_init(g, FALCON_ID_NVDEC);
if (err != 0) {
@@ -272,23 +273,38 @@ static int nvgpu_falcons_sw_init(struct gk20a *g)
goto done_nvdec;
}
#endif
err = g->ops.falcon.falcon_sw_init(g, FALCON_ID_OFA);
if (err != 0) {
nvgpu_err(g, "failed to sw init FALCON_ID_OFA");
goto done_nvenc;
}
err = g->ops.falcon.falcon_sw_init(g, FALCON_ID_NVJPG);
if (err != 0) {
nvgpu_err(g, "failed to sw init FALCON_ID_NVENC");
goto done_ofa;
}
if (g->ops.gsp.is_gsp_supported != false) {
err = g->ops.falcon.falcon_sw_init(g, FALCON_ID_GSPLITE);
if (err != 0) {
nvgpu_err(g, "failed to sw init FALCON_ID_GSPLITE");
goto done_nvenc;
goto done_nvjpg;
}
}
return 0;
done_nvjpg:
g->ops.falcon.falcon_sw_free(g, FALCON_ID_NVJPG);
done_ofa:
g->ops.falcon.falcon_sw_free(g, FALCON_ID_OFA);
done_nvenc:
#ifdef CONFIG_NVGPU_DGPU
g->ops.falcon.falcon_sw_free(g, FALCON_ID_NVENC);
done_nvdec:
g->ops.falcon.falcon_sw_free(g, FALCON_ID_NVDEC);
done_sec2:
#ifdef CONFIG_NVGPU_DGPU
g->ops.falcon.falcon_sw_free(g, FALCON_ID_SEC2);
done_fecs:
#endif
@@ -308,13 +324,15 @@ static void nvgpu_falcons_sw_free(struct gk20a *g)
g->ops.falcon.falcon_sw_free(g, FALCON_ID_PMU);
}
g->ops.falcon.falcon_sw_free(g, FALCON_ID_FECS);
g->ops.falcon.falcon_sw_free(g, FALCON_ID_NVENC);
g->ops.falcon.falcon_sw_free(g, FALCON_ID_OFA);
g->ops.falcon.falcon_sw_free(g, FALCON_ID_NVDEC);
g->ops.falcon.falcon_sw_free(g, FALCON_ID_NVJPG);
#ifdef CONFIG_NVGPU_DGPU
if (g->ops.gsp.is_gsp_supported != false) {
g->ops.falcon.falcon_sw_free(g, FALCON_ID_GSPLITE);
}
g->ops.falcon.falcon_sw_free(g, FALCON_ID_NVDEC);
g->ops.falcon.falcon_sw_free(g, FALCON_ID_NVENC);
g->ops.falcon.falcon_sw_free(g, FALCON_ID_SEC2);
#endif
}

4
drivers/gpu/nvgpu/hal/falcon/falcon_ga10b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -31,7 +31,7 @@ u32 ga10b_falcon_get_mem_size(struct nvgpu_falcon *flcn,
enum falcon_mem_type mem_type);
bool ga10b_falcon_is_cpu_halted(struct nvgpu_falcon *flcn);
void ga10b_falcon_set_bcr(struct nvgpu_falcon *flcn);
void ga10b_falcon_bootstrap(struct nvgpu_falcon *flcn, u32 boot_vector);
void ga10b_falcon_bootstrap(struct nvgpu_falcon *flcn, u64 boot_vector);
void ga10b_falcon_dump_brom_stats(struct nvgpu_falcon *flcn);
u32 ga10b_falcon_get_brom_retcode(struct nvgpu_falcon *flcn);
bool ga10b_falcon_is_priv_lockdown(struct nvgpu_falcon *flcn);

15
drivers/gpu/nvgpu/hal/falcon/falcon_ga10b_fusa.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -56,21 +56,28 @@ void ga10b_falcon_set_bcr(struct nvgpu_falcon *flcn)
nvgpu_riscv_writel(flcn, priscv_priscv_bcr_ctrl_r(), 0x11);
}
void ga10b_falcon_bootstrap(struct nvgpu_falcon *flcn, u32 boot_vector)
void ga10b_falcon_bootstrap(struct nvgpu_falcon *flcn, u64 boot_vector)
{
/* Need to check this through fuse/SW policy*/
if (flcn->is_falcon2_enabled) {
nvgpu_log_info(flcn->g, "boot riscv core");
if (boot_vector != 0U) {
nvgpu_log_info(flcn->g, "riscv boot vec 0x%llx", boot_vector);
nvgpu_riscv_writel(flcn, priscv_riscv_boot_vector_lo_r(),
u64_lo32(boot_vector));
nvgpu_riscv_writel(flcn, priscv_riscv_boot_vector_hi_r(),
u64_hi32(boot_vector));
}
nvgpu_riscv_writel(flcn, priscv_priscv_cpuctl_r(),
priscv_priscv_cpuctl_startcpu_true_f());
} else {
nvgpu_log_info(flcn->g, "falcon boot vec 0x%x", boot_vector);
nvgpu_log_info(flcn->g, "falcon boot vec 0x%llx", boot_vector);
nvgpu_falcon_writel(flcn, falcon_falcon_dmactl_r(),
falcon_falcon_dmactl_require_ctx_f(0));
nvgpu_falcon_writel(flcn, falcon_falcon_bootvec_r(),
falcon_falcon_bootvec_vec_f(boot_vector));
falcon_falcon_bootvec_vec_f(nvgpu_safe_cast_u64_to_u32(boot_vector)));
nvgpu_falcon_writel(flcn, falcon_falcon_cpuctl_r(),
falcon_falcon_cpuctl_startcpu_f(1));

2
drivers/gpu/nvgpu/hal/falcon/falcon_gk20a.h
View File

@@ -76,7 +76,7 @@ int gk20a_falcon_copy_to_dmem(struct nvgpu_falcon *flcn,
int gk20a_falcon_copy_to_imem(struct nvgpu_falcon *flcn, u32 dst,
u8 *src, u32 size, u8 port, bool sec, u32 tag);
void gk20a_falcon_bootstrap(struct nvgpu_falcon *flcn,
u32 boot_vector);
u64 boot_vector);
u32 gk20a_falcon_mailbox_read(struct nvgpu_falcon *flcn,
u32 mailbox_index);
void gk20a_falcon_mailbox_write(struct nvgpu_falcon *flcn,

6
drivers/gpu/nvgpu/hal/falcon/falcon_gk20a_fusa.c
View File

@@ -355,15 +355,15 @@ NVGPU_COV_WHITELIST(deviate, NVGPU_MISRA(Rule, 11_3), "TID-415")
}
void gk20a_falcon_bootstrap(struct nvgpu_falcon *flcn,
u32 boot_vector)
u64 boot_vector)
{
nvgpu_log_info(flcn->g, "boot vec 0x%x", boot_vector);
nvgpu_log_info(flcn->g, "boot vec 0x%llx", boot_vector);
nvgpu_falcon_writel(flcn, falcon_falcon_dmactl_r(),
falcon_falcon_dmactl_require_ctx_f(0));
nvgpu_falcon_writel(flcn, falcon_falcon_bootvec_r(),
falcon_falcon_bootvec_vec_f(boot_vector));
falcon_falcon_bootvec_vec_f(nvgpu_safe_cast_u64_to_u32(boot_vector)));
nvgpu_falcon_writel(flcn, falcon_falcon_cpuctl_r(),
falcon_falcon_cpuctl_startcpu_f(1));

6
drivers/gpu/nvgpu/hal/mc/mc_ga10b_fusa.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -116,6 +116,10 @@ static u32 ga10b_mc_unit_reset_mask(struct gk20a *g, u32 unit)
case NVGPU_UNIT_FIFO:
case NVGPU_UNIT_GRAPH:
case NVGPU_UNIT_BLG:
case NVGPU_UNIT_NVENC:
case NVGPU_UNIT_OFA:
case NVGPU_UNIT_NVDEC:
case NVGPU_UNIT_NVJPG:
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
case NVGPU_UNIT_PWR:
#endif

8
drivers/gpu/nvgpu/include/nvgpu/falcon.h
View File

@@ -126,14 +126,18 @@
#define FALCON_ID_GPCCS (3U)
/** Falcon ID for NVDEC engine */
#define FALCON_ID_NVDEC (4U)
/** Falcon ID for NVDEC engine */
/** Falcon ID for NVENC engine */
#define FALCON_ID_NVENC (5U)
/** Falcon ID for SEC2 engine */
#define FALCON_ID_SEC2 (7U)
/** Falcon ID for MINION engine */
#define FALCON_ID_MINION (10U)
#define FALCON_ID_PMU_NEXT_CORE (13U)
#define FALCON_ID_END (15U)
/** Falcon ID for OFA engine */
#define FALCON_ID_OFA (15U)
/** Falcon ID for NVJPG engine */
#define FALCON_ID_NVJPG (16U)
#define FALCON_ID_END (17U)
#define FALCON_ID_INVALID 0xFFFFFFFFU
#define FALCON_MAILBOX_0 0x0U

7
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -516,8 +516,13 @@ struct gk20a {
struct nvgpu_falcon gpccs_flcn;
/** Struct holding the nvenc falcon software state. */
struct nvgpu_falcon nvenc_flcn;
#ifdef CONFIG_NVGPU_DGPU
/** Struct holding the ofa falcon software state. */
struct nvgpu_falcon ofa_flcn;
/** Struct holding the nvdec falcon software state. */
struct nvgpu_falcon nvdec_flcn;
/** Struct holding the nvjpg falcon software state. */
struct nvgpu_falcon nvjpg_flcn;
#ifdef CONFIG_NVGPU_DGPU
struct nvgpu_falcon minion_flcn;
#endif
#ifdef CONFIG_NVGPU_NON_FUSA

3
drivers/gpu/nvgpu/include/nvgpu/gops/falcon.h
View File

@@ -61,7 +61,7 @@ struct gops_falcon {
u64 fmc_data_addr, u64 manifest_addr);
u32 (*imemc_blk_field)(u32 blk);
void (*bootstrap)(struct nvgpu_falcon *flcn,
u32 boot_vector);
u64 boot_vector);
u32 (*mailbox_read)(struct nvgpu_falcon *flcn,
u32 mailbox_index);
void (*mailbox_write)(struct nvgpu_falcon *flcn,
@@ -86,6 +86,7 @@ struct gops_falcon {
int (*load_ucode)(struct nvgpu_falcon *flcn,
struct nvgpu_mem *mem_desc, u32 *ucode_header);
u32 (*debuginfo_offset)(void);
/** @endcond DOXYGEN_SHOULD_SKIP_THIS */

4
drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_priscv_ga10b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -78,4 +78,6 @@
#define priscv_priscv_bcr_dmacfg_lock_locked_f() (0x80000000U)
#define priscv_riscv_irqmask_r() (0x00000528U)
#define priscv_riscv_irqdest_r() (0x0000052cU)
#define priscv_riscv_boot_vector_lo_r() (0x00000380U)
#define priscv_riscv_boot_vector_hi_r() (0x00000384U)
#endif