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0526e7eaa9
common.cic unit is divided into common.cic.mon and common.cic.rm based on rm and mon process split. CIC-mon subunit includes the code which is utilized in critical interrupt handling path like initialization, error detection and error reporting path. CIC-rm subunit includes the code corresponding to rest of interrupt handling(like collecting error debug data from registers) and ISR status management (status of deferred interrupts). Split the CIC APIs and data-members into above two subunits. JIRA NVGPU-6899 Change-Id: I151b59105ff570607c4a62e974785e9c1323ef69 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2551897 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
107 lines
3.0 KiB
C
107 lines
3.0 KiB
C
/*
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* GK20A Graphics FIFO (gr host)
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*
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* Copyright (c) 2011-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/log.h>
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#include <nvgpu/soc.h>
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#include <nvgpu/io.h>
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#include <nvgpu/fifo.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/power_features/cg.h>
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#include <nvgpu/cic_mon.h>
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#include <nvgpu/mc.h>
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#include "hal/fifo/fifo_gk20a.h"
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#include <nvgpu/hw/gk20a/hw_fifo_gk20a.h>
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static void enable_fifo_interrupts(struct gk20a *g)
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{
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nvgpu_cic_mon_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_FIFO, NVGPU_CIC_INTR_ENABLE);
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nvgpu_cic_mon_intr_nonstall_unit_config(g, NVGPU_CIC_INTR_UNIT_FIFO,
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NVGPU_CIC_INTR_ENABLE);
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g->ops.fifo.intr_0_enable(g, true);
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g->ops.fifo.intr_1_enable(g, true);
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}
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int gk20a_init_fifo_reset_enable_hw(struct gk20a *g)
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{
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u32 timeout;
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int err;
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nvgpu_log_fn(g, " ");
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/* enable pmc pfifo */
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err = nvgpu_mc_reset_units(g, NVGPU_UNIT_FIFO);
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if (err != 0) {
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nvgpu_err(g, "Failed to reset FIFO unit");
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}
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nvgpu_cg_slcg_fifo_load_enable(g);
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nvgpu_cg_blcg_fifo_load_enable(g);
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timeout = nvgpu_readl(g, fifo_fb_timeout_r());
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timeout = set_field(timeout, fifo_fb_timeout_period_m(),
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fifo_fb_timeout_period_max_f());
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nvgpu_log_info(g, "fifo_fb_timeout reg val = 0x%08x", timeout);
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nvgpu_writel(g, fifo_fb_timeout_r(), timeout);
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g->ops.pbdma.setup_hw(g);
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enable_fifo_interrupts(g);
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nvgpu_log_fn(g, "done");
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return 0;
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}
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int gk20a_init_fifo_setup_hw(struct gk20a *g)
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{
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#ifdef CONFIG_NVGPU_USERD
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struct nvgpu_fifo *f = &g->fifo;
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u64 shifted_addr;
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nvgpu_log_fn(g, " ");
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/* set the base for the userd region now */
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shifted_addr = f->userd_gpu_va >> 12;
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if ((shifted_addr >> 32) != 0U) {
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nvgpu_err(g, "GPU VA > 32 bits %016llx", f->userd_gpu_va);
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return -EFAULT;
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}
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nvgpu_writel(g, fifo_bar1_base_r(),
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fifo_bar1_base_ptr_f(u64_lo32(shifted_addr)) |
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fifo_bar1_base_valid_true_f());
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#endif
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nvgpu_log_fn(g, "done");
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return 0;
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}
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void gk20a_fifo_bar1_snooping_disable(struct gk20a *g)
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{
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nvgpu_writel(g, fifo_bar1_base_r(),
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fifo_bar1_base_valid_false_f());
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}
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