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linux-nvgpu/drivers/gpu/nvgpu/common/ecc.c
Deepak Nibade a5eb150635 gpu: nvgpu: add new gr/config unit to initialize GR configuration 
Add new unit gr/config to initialize GR configuration like GPC/TPC
count, MAX count and mask

Create new structure nvgpu_gr_config that stores all the configuration
and that is owned by the new unit

Move below fields from struct gr_gk20a to nvgpu_gr_config in gr/config.h
Struct gr_gk20a now only holds the pointer to struct nvgpu_gr_config

u32 max_gpc_count;
u32 max_tpc_per_gpc_count;
u32 max_zcull_per_gpc_count;
u32 max_tpc_count;

u32 gpc_count;
u32 tpc_count;
u32 ppc_count;
u32 zcb_count;

u32 pe_count_per_gpc;

u32 *gpc_tpc_count;
u32 *gpc_ppc_count;
u32 *gpc_zcb_count;
u32 *pes_tpc_count[GK20A_GR_MAX_PES_PER_GPC];

u32 *gpc_tpc_mask;
u32 *pes_tpc_mask[GK20A_GR_MAX_PES_PER_GPC];
u32 *gpc_skip_mask;

u8 *map_tiles;
u32 map_tile_count;
u32 map_row_offset;

Remove gr->sys_count since it was already no longer used

common/gr/config/gr_config.c unit now exposes the APIs to initialize
the configuration and also to query the configuration values

nvgpu_gr_config_init() is called to initialize GR configuration from
gr_gk20a_init_gr_config() and gr_gk20a_init_map_tiles() is simply
renamed as nvgpu_gr_config_init_map_tiles()

Expose new API nvgpu_gr_config_deinit() to deinit the configuration

Expose nvgpu_gr_config_get_*() APIs to query above configuration
fields stored in nvgpu_gr_config structure

Update vgpu_gr_init_gr_config() to initialize the configuration
from gr->config structure

Chip specific HALs that access GR register for initialization
are implemented in common/gr/config/gr_config_gm20b.c
Set these HALs for all GPUs

Jira NVGPU-1879

Change-Id: Ided658b43124ea61b9f273b82b73fdde4ed3c8f0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2012167
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-02-08 12:55:53 -08:00

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/*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/gk20a.h>
#include <nvgpu/gr/config.h>
static void nvgpu_ecc_stat_add(struct gk20a *g, struct nvgpu_ecc_stat *stat)
{
struct nvgpu_ecc *ecc = &g->ecc;
nvgpu_init_list_node(&stat->node);
nvgpu_list_add_tail(&stat->node, &ecc->stats_list);
ecc->stats_count++;
}
static void nvgpu_ecc_init(struct gk20a *g)
{
struct nvgpu_ecc *ecc = &g->ecc;
nvgpu_init_list_node(&ecc->stats_list);
}
int nvgpu_ecc_counter_init_per_tpc(struct gk20a *g,
struct nvgpu_ecc_stat ***stat, const char *name)
{
struct gr_gk20a *gr = &g->gr;
struct nvgpu_ecc_stat **stats;
u32 gpc_count = nvgpu_gr_config_get_gpc_count(gr->config);
u32 gpc, tpc;
int err = 0;
stats = nvgpu_kzalloc(g, sizeof(*stats) * gpc_count);
if (stats == NULL) {
return -ENOMEM;
}
for (gpc = 0; gpc < gpc_count; gpc++) {
stats[gpc] = nvgpu_kzalloc(g, sizeof(*stats[gpc]) *
nvgpu_gr_config_get_gpc_tpc_count(gr->config, gpc));
if (stats[gpc] == NULL) {
err = -ENOMEM;
break;
}
}
if (err != 0) {
while (gpc-- != 0u) {
nvgpu_kfree(g, stats[gpc]);
}
nvgpu_kfree(g, stats);
return err;
}
for (gpc = 0; gpc < gpc_count; gpc++) {
for (tpc = 0;
tpc < nvgpu_gr_config_get_gpc_tpc_count(gr->config, gpc);
tpc++) {
(void) snprintf(stats[gpc][tpc].name,
NVGPU_ECC_STAT_NAME_MAX_SIZE,
"gpc%d_tpc%d_%s", gpc, tpc, name);
nvgpu_ecc_stat_add(g, &stats[gpc][tpc]);
}
}
*stat = stats;
return 0;
}
int nvgpu_ecc_counter_init_per_gpc(struct gk20a *g,
struct nvgpu_ecc_stat **stat, const char *name)
{
struct gr_gk20a *gr = &g->gr;
struct nvgpu_ecc_stat *stats;
u32 gpc_count = nvgpu_gr_config_get_gpc_count(gr->config);
u32 gpc;
stats = nvgpu_kzalloc(g, sizeof(*stats) * gpc_count);
if (stats == NULL) {
return -ENOMEM;
}
for (gpc = 0; gpc < gpc_count; gpc++) {
(void) snprintf(stats[gpc].name, NVGPU_ECC_STAT_NAME_MAX_SIZE,
"gpc%d_%s", gpc, name);
nvgpu_ecc_stat_add(g, &stats[gpc]);
}
*stat = stats;
return 0;
}
int nvgpu_ecc_counter_init(struct gk20a *g,
struct nvgpu_ecc_stat **stat, const char *name)
{
struct nvgpu_ecc_stat *stats;
stats = nvgpu_kzalloc(g, sizeof(*stats));
if (stats == NULL) {
return -ENOMEM;
}
(void)strncpy(stats->name, name, NVGPU_ECC_STAT_NAME_MAX_SIZE - 1);
nvgpu_ecc_stat_add(g, stats);
*stat = stats;
return 0;
}
int nvgpu_ecc_counter_init_per_lts(struct gk20a *g,
struct nvgpu_ecc_stat ***stat, const char *name)
{
struct gr_gk20a *gr = &g->gr;
struct nvgpu_ecc_stat **stats;
u32 ltc, lts;
int err = 0;
stats = nvgpu_kzalloc(g, sizeof(*stats) * g->ltc_count);
if (stats == NULL) {
return -ENOMEM;
}
for (ltc = 0; ltc < g->ltc_count; ltc++) {
stats[ltc] = nvgpu_kzalloc(g,
sizeof(*stats[ltc]) * gr->slices_per_ltc);
if (stats[ltc] == NULL) {
err = -ENOMEM;
break;
}
}
if (err != 0) {
while (ltc-- > 0u) {
nvgpu_kfree(g, stats[ltc]);
}
nvgpu_kfree(g, stats);
return err;
}
for (ltc = 0; ltc < g->ltc_count; ltc++) {
for (lts = 0; lts < gr->slices_per_ltc; lts++) {
(void) snprintf(stats[ltc][lts].name,
NVGPU_ECC_STAT_NAME_MAX_SIZE,
"ltc%d_lts%d_%s", ltc, lts, name);
nvgpu_ecc_stat_add(g, &stats[ltc][lts]);
}
}
*stat = stats;
return 0;
}
int nvgpu_ecc_counter_init_per_fbpa(struct gk20a *g,
struct nvgpu_ecc_stat **stat, const char *name)
{
int i;
int num_fbpa = nvgpu_get_litter_value(g, GPU_LIT_NUM_FBPAS);
struct nvgpu_ecc_stat *stats;
stats = nvgpu_kzalloc(g, sizeof(*stats) * (size_t)num_fbpa);
if (stats == NULL) {
return -ENOMEM;
}
for (i = 0; i < num_fbpa; i++) {
(void) snprintf(stats[i].name, NVGPU_ECC_STAT_NAME_MAX_SIZE,
"fbpa%d_%s", i, name);
nvgpu_ecc_stat_add(g, &stats[i]);
}
*stat = stats;
return 0;
}
/* release all ecc_stat */
void nvgpu_ecc_free(struct gk20a *g)
{
struct nvgpu_ecc *ecc = &g->ecc;
struct gr_gk20a *gr = &g->gr;
u32 gpc_count = nvgpu_gr_config_get_gpc_count(gr->config);
u32 i;
for (i = 0; i < gpc_count; i++) {
if (ecc->gr.sm_lrf_ecc_single_err_count != NULL) {
nvgpu_kfree(g, ecc->gr.sm_lrf_ecc_single_err_count[i]);
}
if (ecc->gr.sm_lrf_ecc_double_err_count != NULL) {
nvgpu_kfree(g, ecc->gr.sm_lrf_ecc_double_err_count[i]);
}
if (ecc->gr.sm_shm_ecc_sec_count != NULL) {
nvgpu_kfree(g, ecc->gr.sm_shm_ecc_sec_count[i]);
}
if (ecc->gr.sm_shm_ecc_sed_count != NULL) {
nvgpu_kfree(g, ecc->gr.sm_shm_ecc_sed_count[i]);
}
if (ecc->gr.sm_shm_ecc_ded_count != NULL) {
nvgpu_kfree(g, ecc->gr.sm_shm_ecc_ded_count[i]);
}
if (ecc->gr.tex_ecc_total_sec_pipe0_count != NULL) {
nvgpu_kfree(g, ecc->gr.tex_ecc_total_sec_pipe0_count[i]);
}
if (ecc->gr.tex_ecc_total_ded_pipe0_count != NULL) {
nvgpu_kfree(g, ecc->gr.tex_ecc_total_ded_pipe0_count[i]);
}
if (ecc->gr.tex_unique_ecc_sec_pipe0_count != NULL) {
nvgpu_kfree(g, ecc->gr.tex_unique_ecc_sec_pipe0_count[i]);
}
if (ecc->gr.tex_unique_ecc_ded_pipe0_count != NULL) {
nvgpu_kfree(g, ecc->gr.tex_unique_ecc_ded_pipe0_count[i]);
}
if (ecc->gr.tex_ecc_total_sec_pipe1_count != NULL) {
nvgpu_kfree(g, ecc->gr.tex_ecc_total_sec_pipe1_count[i]);
}
if (ecc->gr.tex_ecc_total_ded_pipe1_count != NULL) {
nvgpu_kfree(g, ecc->gr.tex_ecc_total_ded_pipe1_count[i]);
}
if (ecc->gr.tex_unique_ecc_sec_pipe1_count != NULL) {
nvgpu_kfree(g, ecc->gr.tex_unique_ecc_sec_pipe1_count[i]);
}
if (ecc->gr.tex_unique_ecc_ded_pipe1_count != NULL) {
nvgpu_kfree(g, ecc->gr.tex_unique_ecc_ded_pipe1_count[i]);
}
if (ecc->gr.sm_l1_tag_ecc_corrected_err_count != NULL) {
nvgpu_kfree(g, ecc->gr.sm_l1_tag_ecc_corrected_err_count[i]);
}
if (ecc->gr.sm_l1_tag_ecc_uncorrected_err_count != NULL) {
nvgpu_kfree(g, ecc->gr.sm_l1_tag_ecc_uncorrected_err_count[i]);
}
if (ecc->gr.sm_cbu_ecc_corrected_err_count != NULL) {
nvgpu_kfree(g, ecc->gr.sm_cbu_ecc_corrected_err_count[i]);
}
if (ecc->gr.sm_cbu_ecc_uncorrected_err_count != NULL) {
nvgpu_kfree(g, ecc->gr.sm_cbu_ecc_uncorrected_err_count[i]);
}
if (ecc->gr.sm_l1_data_ecc_corrected_err_count != NULL) {
nvgpu_kfree(g, ecc->gr.sm_l1_data_ecc_corrected_err_count[i]);
}
if (ecc->gr.sm_l1_data_ecc_uncorrected_err_count != NULL) {
nvgpu_kfree(g, ecc->gr.sm_l1_data_ecc_uncorrected_err_count[i]);
}
if (ecc->gr.sm_icache_ecc_corrected_err_count != NULL) {
nvgpu_kfree(g, ecc->gr.sm_icache_ecc_corrected_err_count[i]);
}
if (ecc->gr.sm_icache_ecc_uncorrected_err_count != NULL) {
nvgpu_kfree(g, ecc->gr.sm_icache_ecc_uncorrected_err_count[i]);
}
}
nvgpu_kfree(g, ecc->gr.sm_lrf_ecc_single_err_count);
nvgpu_kfree(g, ecc->gr.sm_lrf_ecc_double_err_count);
nvgpu_kfree(g, ecc->gr.sm_shm_ecc_sec_count);
nvgpu_kfree(g, ecc->gr.sm_shm_ecc_sed_count);
nvgpu_kfree(g, ecc->gr.sm_shm_ecc_ded_count);
nvgpu_kfree(g, ecc->gr.tex_ecc_total_sec_pipe0_count);
nvgpu_kfree(g, ecc->gr.tex_ecc_total_ded_pipe0_count);
nvgpu_kfree(g, ecc->gr.tex_unique_ecc_sec_pipe0_count);
nvgpu_kfree(g, ecc->gr.tex_unique_ecc_ded_pipe0_count);
nvgpu_kfree(g, ecc->gr.tex_ecc_total_sec_pipe1_count);
nvgpu_kfree(g, ecc->gr.tex_ecc_total_ded_pipe1_count);
nvgpu_kfree(g, ecc->gr.tex_unique_ecc_sec_pipe1_count);
nvgpu_kfree(g, ecc->gr.tex_unique_ecc_ded_pipe1_count);
nvgpu_kfree(g, ecc->gr.sm_l1_tag_ecc_corrected_err_count);
nvgpu_kfree(g, ecc->gr.sm_l1_tag_ecc_uncorrected_err_count);
nvgpu_kfree(g, ecc->gr.sm_cbu_ecc_corrected_err_count);
nvgpu_kfree(g, ecc->gr.sm_cbu_ecc_uncorrected_err_count);
nvgpu_kfree(g, ecc->gr.sm_l1_data_ecc_corrected_err_count);
nvgpu_kfree(g, ecc->gr.sm_l1_data_ecc_uncorrected_err_count);
nvgpu_kfree(g, ecc->gr.sm_icache_ecc_corrected_err_count);
nvgpu_kfree(g, ecc->gr.sm_icache_ecc_uncorrected_err_count);
nvgpu_kfree(g, ecc->gr.gcc_l15_ecc_corrected_err_count);
nvgpu_kfree(g, ecc->gr.gcc_l15_ecc_uncorrected_err_count);
nvgpu_kfree(g, ecc->gr.gpccs_ecc_corrected_err_count);
nvgpu_kfree(g, ecc->gr.gpccs_ecc_uncorrected_err_count);
nvgpu_kfree(g, ecc->gr.mmu_l1tlb_ecc_corrected_err_count);
nvgpu_kfree(g, ecc->gr.mmu_l1tlb_ecc_uncorrected_err_count);
nvgpu_kfree(g, ecc->gr.fecs_ecc_corrected_err_count);
nvgpu_kfree(g, ecc->gr.fecs_ecc_uncorrected_err_count);
for (i = 0; i < g->ltc_count; i++) {
if (ecc->ltc.ecc_sec_count != NULL) {
nvgpu_kfree(g, ecc->ltc.ecc_sec_count[i]);
}
if (ecc->ltc.ecc_ded_count != NULL) {
nvgpu_kfree(g, ecc->ltc.ecc_ded_count[i]);
}
}
nvgpu_kfree(g, ecc->ltc.ecc_sec_count);
nvgpu_kfree(g, ecc->ltc.ecc_ded_count);
nvgpu_kfree(g, ecc->fb.mmu_l2tlb_ecc_corrected_err_count);
nvgpu_kfree(g, ecc->fb.mmu_l2tlb_ecc_uncorrected_err_count);
nvgpu_kfree(g, ecc->fb.mmu_hubtlb_ecc_corrected_err_count);
nvgpu_kfree(g, ecc->fb.mmu_hubtlb_ecc_uncorrected_err_count);
nvgpu_kfree(g, ecc->fb.mmu_fillunit_ecc_corrected_err_count);
nvgpu_kfree(g, ecc->fb.mmu_fillunit_ecc_uncorrected_err_count);
nvgpu_kfree(g, ecc->pmu.pmu_ecc_corrected_err_count);
nvgpu_kfree(g, ecc->pmu.pmu_ecc_uncorrected_err_count);
nvgpu_kfree(g, ecc->fbpa.fbpa_ecc_sec_err_count);
nvgpu_kfree(g, ecc->fbpa.fbpa_ecc_ded_err_count);
(void)memset(ecc, 0, sizeof(*ecc));
}
int nvgpu_ecc_init_support(struct gk20a *g)
{
int err;
if (g->ops.gr.init_ecc == NULL) {
return 0;
}
nvgpu_ecc_init(g);
err = g->ops.gr.init_ecc(g);
if (err != 0) {
return err;
}
err = nvgpu_ecc_sysfs_init(g);
if (err != 0) {
nvgpu_ecc_free(g);
return err;
}
return 0;
}
void nvgpu_ecc_remove_support(struct gk20a *g)
{
if (g->ops.gr.init_ecc == NULL) {
return;
}
nvgpu_ecc_sysfs_remove(g);
nvgpu_ecc_free(g);
}
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