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c0668f05ea
Query interrupt number and reset id from HW. Use the number from HW when enabling and detecting interrupts. Bug 200036089 Bug 1567274 Change-Id: If9cb4db79a19dcb193ba7ad9db7081f4fe1ab433 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/600988
148 lines
3.7 KiB
C
148 lines
3.7 KiB
C
/*
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* GK20A memory interface
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*
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* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/types.h>
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#include "gk20a.h"
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#include "mc_gk20a.h"
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#include "hw_mc_gk20a.h"
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irqreturn_t mc_gk20a_isr_stall(struct gk20a *g)
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{
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u32 mc_intr_0;
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if (!g->power_on)
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return IRQ_NONE;
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/* not from gpu when sharing irq with others */
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mc_intr_0 = gk20a_readl(g, mc_intr_0_r());
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if (unlikely(!mc_intr_0))
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return IRQ_NONE;
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gk20a_writel(g, mc_intr_en_0_r(),
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mc_intr_en_0_inta_disabled_f());
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/* flush previous write */
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gk20a_readl(g, mc_intr_en_0_r());
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return IRQ_WAKE_THREAD;
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}
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irqreturn_t mc_gk20a_isr_nonstall(struct gk20a *g)
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{
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u32 mc_intr_1;
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if (!g->power_on)
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return IRQ_NONE;
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/* not from gpu when sharing irq with others */
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mc_intr_1 = gk20a_readl(g, mc_intr_1_r());
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if (unlikely(!mc_intr_1))
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return IRQ_NONE;
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gk20a_writel(g, mc_intr_en_1_r(),
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mc_intr_en_1_inta_disabled_f());
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/* flush previous write */
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gk20a_readl(g, mc_intr_en_1_r());
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return IRQ_WAKE_THREAD;
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}
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irqreturn_t mc_gk20a_intr_thread_stall(struct gk20a *g)
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{
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u32 mc_intr_0;
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gk20a_dbg(gpu_dbg_intr, "interrupt thread launched");
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mc_intr_0 = gk20a_readl(g, mc_intr_0_r());
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gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0);
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if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id))
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gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g));
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if (mc_intr_0 & mc_intr_0_pfifo_pending_f())
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gk20a_fifo_isr(g);
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if (mc_intr_0 & mc_intr_0_pmu_pending_f())
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gk20a_pmu_isr(g);
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if (mc_intr_0 & mc_intr_0_priv_ring_pending_f())
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gk20a_priv_ring_isr(g);
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if (mc_intr_0 & mc_intr_0_ltc_pending_f())
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g->ops.ltc.isr(g);
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if (mc_intr_0 & mc_intr_0_pbus_pending_f())
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gk20a_pbus_isr(g);
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gk20a_writel(g, mc_intr_en_0_r(),
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mc_intr_en_0_inta_hardware_f());
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/* flush previous write */
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gk20a_readl(g, mc_intr_en_0_r());
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return IRQ_HANDLED;
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}
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irqreturn_t mc_gk20a_intr_thread_nonstall(struct gk20a *g)
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{
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u32 mc_intr_1;
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gk20a_dbg(gpu_dbg_intr, "interrupt thread launched");
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mc_intr_1 = gk20a_readl(g, mc_intr_1_r());
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gk20a_dbg(gpu_dbg_intr, "non-stall intr %08x\n", mc_intr_1);
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if (mc_intr_1 & mc_intr_0_pfifo_pending_f())
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gk20a_fifo_nonstall_isr(g);
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if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id))
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gk20a_gr_nonstall_isr(g);
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gk20a_writel(g, mc_intr_en_1_r(),
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mc_intr_en_1_inta_hardware_f());
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/* flush previous write */
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gk20a_readl(g, mc_intr_en_1_r());
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return IRQ_HANDLED;
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}
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void mc_gk20a_intr_enable(struct gk20a *g)
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{
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u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g);
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gk20a_writel(g, mc_intr_mask_1_r(),
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mc_intr_0_pfifo_pending_f()
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| eng_intr_mask);
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gk20a_writel(g, mc_intr_en_1_r(),
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mc_intr_en_1_inta_hardware_f());
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gk20a_writel(g, mc_intr_mask_0_r(),
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mc_intr_0_pfifo_pending_f()
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| mc_intr_0_priv_ring_pending_f()
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| mc_intr_0_ltc_pending_f()
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| mc_intr_0_pbus_pending_f()
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| eng_intr_mask);
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gk20a_writel(g, mc_intr_en_0_r(),
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mc_intr_en_0_inta_hardware_f());
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}
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void gk20a_init_mc(struct gpu_ops *gops)
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{
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gops->mc.intr_enable = mc_gk20a_intr_enable;
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gops->mc.isr_stall = mc_gk20a_isr_stall;
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gops->mc.isr_nonstall = mc_gk20a_isr_nonstall;
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gops->mc.isr_thread_stall = mc_gk20a_intr_thread_stall;
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gops->mc.isr_thread_nonstall = mc_gk20a_intr_thread_nonstall;
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}
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