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c3fa78b1d9
Begin moving (and renaming) the GMMU code into common/mm/gmmu.c. This block of code will be responsible for handling the platform/OS independent GMMU operations. JIRA NVGPU-12 JIRA NVGPU-30 Change-Id: Ide761bab75e5d84be3dcb977c4842ae4b3a7c1b3 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1464083 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
110 lines
2.8 KiB
C
110 lines
2.8 KiB
C
/*
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <nvgpu/log.h>
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#include <nvgpu/gmmu.h>
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#include <nvgpu/nvgpu_mem.h>
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#include "gk20a/gk20a.h"
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#include "gk20a/mm_gk20a.h"
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/*
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* Core GMMU map function for the kernel to use. If @addr is 0 then the GPU
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* VA will be allocated for you. If addr is non-zero then the buffer will be
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* mapped at @addr.
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*/
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static u64 __nvgpu_gmmu_map(struct vm_gk20a *vm,
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struct nvgpu_mem *mem,
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u64 addr,
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u64 size,
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u32 flags,
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int rw_flag,
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bool priv,
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enum nvgpu_aperture aperture)
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{
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struct gk20a *g = gk20a_from_vm(vm);
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u64 vaddr;
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struct sg_table *sgt = mem->priv.sgt;
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nvgpu_mutex_acquire(&vm->update_gmmu_lock);
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vaddr = g->ops.mm.gmmu_map(vm, addr,
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sgt, /* sg table */
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0, /* sg offset */
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size,
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gmmu_page_size_kernel,
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0, /* kind */
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0, /* ctag_offset */
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flags, rw_flag,
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false, /* clear_ctags */
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false, /* sparse */
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priv, /* priv */
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NULL, /* mapping_batch handle */
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aperture);
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nvgpu_mutex_release(&vm->update_gmmu_lock);
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if (!vaddr) {
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nvgpu_err(g, "failed to allocate va space");
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return 0;
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}
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return vaddr;
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}
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u64 nvgpu_gmmu_map(struct vm_gk20a *vm,
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struct nvgpu_mem *mem,
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u64 size,
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u32 flags,
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int rw_flag,
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bool priv,
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enum nvgpu_aperture aperture)
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{
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return __nvgpu_gmmu_map(vm, mem, 0, size, flags, rw_flag, priv,
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aperture);
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}
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/*
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* Like nvgpu_gmmu_map() except it can work on a fixed address instead.
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*/
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u64 nvgpu_gmmu_map_fixed(struct vm_gk20a *vm,
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struct nvgpu_mem *mem,
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u64 addr,
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u64 size,
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u32 flags,
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int rw_flag,
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bool priv,
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enum nvgpu_aperture aperture)
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{
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return __nvgpu_gmmu_map(vm, mem, addr, size, flags, rw_flag, priv,
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aperture);
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}
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void nvgpu_gmmu_unmap(struct vm_gk20a *vm, struct nvgpu_mem *mem, u64 gpu_va)
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{
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struct gk20a *g = gk20a_from_vm(vm);
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nvgpu_mutex_acquire(&vm->update_gmmu_lock);
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g->ops.mm.gmmu_unmap(vm,
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gpu_va,
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mem->size,
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gmmu_page_size_kernel,
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true, /*va_allocated */
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gk20a_mem_flag_none,
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false,
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NULL);
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nvgpu_mutex_release(&vm->update_gmmu_lock);
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}
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