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c48bfdd0d6
gk20a_fifo_pbdma_fault_rc is moved to common.rc unit and renamed to nvgpu_rc_pbdma_fault. The function is modified such that when the pbdma id is a channel, recovery is issued only when the channel is part of a valid tsg. Jira NVGPU-2950 Change-Id: I5e975cf79810479f83ffd50581c214a64d1619a6 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2083749 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
87 lines
3.0 KiB
C
87 lines
3.0 KiB
C
/*
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* Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/log.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/fifo.h>
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#include <nvgpu/channel.h>
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#include <nvgpu/tsg.h>
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#include <nvgpu/error_notifier.h>
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#include <nvgpu/nvgpu_err.h>
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#include <nvgpu/pbdma_status.h>
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#include <nvgpu/rc.h>
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#include "gk20a/fifo_gk20a.h"
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void nvgpu_rc_ctxsw_timeout(struct gk20a *g, u32 eng_bitmask,
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struct tsg_gk20a *tsg, bool debug_dump)
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{
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nvgpu_tsg_set_error_notifier(g, tsg,
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NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT);
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/*
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* Cancel all channels' wdt since ctxsw timeout might
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* trigger multiple watchdogs at a time
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*/
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nvgpu_channel_wdt_restart_all_channels(g);
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gk20a_fifo_recover(g, eng_bitmask, tsg->tsgid, true, true, debug_dump,
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RC_TYPE_CTXSW_TIMEOUT);
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}
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void nvgpu_rc_pbdma_fault(struct gk20a *g, struct fifo_gk20a *f,
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u32 pbdma_id, u32 error_notifier)
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{
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u32 id;
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struct nvgpu_pbdma_status_info pbdma_status;
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nvgpu_log(g, gpu_dbg_info, "pbdma id %d error notifier %d",
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pbdma_id, error_notifier);
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g->ops.pbdma_status.read_pbdma_status_info(g, pbdma_id,
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&pbdma_status);
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/* Remove channel from runlist */
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id = pbdma_status.id;
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if (pbdma_status.id_type == PBDMA_STATUS_ID_TYPE_TSGID) {
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struct tsg_gk20a *tsg = &f->tsg[id];
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nvgpu_tsg_set_error_notifier(g, tsg, error_notifier);
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nvgpu_tsg_recover(g, tsg, true, RC_TYPE_PBDMA_FAULT);
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} else if(pbdma_status.id_type == PBDMA_STATUS_ID_TYPE_CHID) {
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struct channel_gk20a *ch = gk20a_channel_from_id(g, id);
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struct tsg_gk20a *tsg;
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if (ch == NULL) {
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nvgpu_err(g, "channel is not referenceable");
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return;
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}
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tsg = tsg_gk20a_from_ch(ch);
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if (tsg != NULL) {
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nvgpu_tsg_set_error_notifier(g, tsg, error_notifier);
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nvgpu_tsg_recover(g, tsg, true, RC_TYPE_PBDMA_FAULT);
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} else {
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nvgpu_err(g, "chid: %d is not bound to tsg", ch->chid);
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}
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gk20a_channel_put(ch);
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} else {
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nvgpu_err(g, "Invalid pbdma_status.id_type");
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}
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} |