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911d25dda2
sema cmdbuf specific functions are only for the sync functionality of nvgpu and donot belong to fifo. construct files sema_cmdbuf_gv11b.h and sema_cmdbuf_gv11b.c under common/sync to contain the syncpt specific cmdbuf functions for arch gv11b. Jira NVGPU-1308 Change-Id: I440847e8b996e0956d81fe6cdde331937deda40e Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1975923 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
79 lines
2.6 KiB
C
79 lines
2.6 KiB
C
/*
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* GV11B sema cmdbuf
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*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/nvgpu_mem.h>
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#include <nvgpu/semaphore.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/channel.h>
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#include "sema_cmdbuf_gv11b.h"
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u32 gv11b_get_sema_wait_cmd_size(void)
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{
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return 10U;
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}
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u32 gv11b_get_sema_incr_cmd_size(void)
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{
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return 12U;
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}
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void gv11b_add_sema_cmd(struct gk20a *g,
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struct nvgpu_semaphore *s, u64 sema_va,
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struct priv_cmd_entry *cmd,
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u32 off, bool acquire, bool wfi)
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{
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nvgpu_log_fn(g, " ");
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/* sema_addr_lo */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010017);
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nvgpu_mem_wr32(g, cmd->mem, off++, sema_va & 0xffffffffULL);
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/* sema_addr_hi */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010018);
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nvgpu_mem_wr32(g, cmd->mem, off++, (sema_va >> 32ULL) & 0xffULL);
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/* payload_lo */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010019);
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nvgpu_mem_wr32(g, cmd->mem, off++, nvgpu_semaphore_get_value(s));
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/* payload_hi : ignored */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001a);
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nvgpu_mem_wr32(g, cmd->mem, off++, 0);
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if (acquire) {
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/* sema_execute : acq_strict_geq | switch_en | 32bit */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001b);
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nvgpu_mem_wr32(g, cmd->mem, off++, U32(0x2) | BIT32(12));
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} else {
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/* sema_execute : release | wfi | 32bit */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001b);
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nvgpu_mem_wr32(g, cmd->mem, off++,
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U32(0x1) | ((wfi ? U32(0x1) : U32(0x0)) << 20U));
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/* non_stall_int : payload is ignored */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010008);
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nvgpu_mem_wr32(g, cmd->mem, off++, 0);
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}
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} |