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gpu: nvgpu: move sema specific cmdbuf methods to common/sync/

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sema cmdbuf specific functions are only for the sync functionality
of nvgpu and donot belong to fifo.

construct files sema_cmdbuf_gv11b.h and sema_cmdbuf_gv11b.c
under common/sync to contain the syncpt specific cmdbuf functions
for arch gv11b.

Jira NVGPU-1308

Change-Id: I440847e8b996e0956d81fe6cdde331937deda40e
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1975923
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Debarshi Dutta
2018-12-19 12:58:17 +05:30
committed by mobile promotions
parent 20b15e6f40
commit 911d25dda2
10 changed files with 135 additions and 67 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/nvgpu/Makefile
View File

@@ -61,6 +61,7 @@ nvgpu-y += common/bus/bus_gk20a.o \
common/sync/channel_sync.o \
common/sync/channel_sync_semaphore.o \
common/sync/sema_cmdbuf_gk20a.o \
common/sync/sema_cmdbuf_gv11b.o \
common/boardobj/boardobj.o \
common/boardobj/boardobjgrp.o \
common/boardobj/boardobjgrpmask.o \

1
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -163,6 +163,7 @@ srcs += common/sim.c \
common/sync/syncpt_cmdbuf_gk20a.c \
common/sync/syncpt_cmdbuf_gv11b.c \
common/sync/sema_cmdbuf_gk20a.c \
common/sync/sema_cmdbuf_gv11b.c \
common/clock_gating/gm20b_gating_reglist.c \
common/clock_gating/gp10b_gating_reglist.c \
common/clock_gating/gv11b_gating_reglist.c \

79
drivers/gpu/nvgpu/common/sync/sema_cmdbuf_gv11b.c Normal file
View File

@@ -0,0 +1,79 @@
/*
* GV11B sema cmdbuf
*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/nvgpu_mem.h>
#include <nvgpu/semaphore.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/channel.h>
#include "sema_cmdbuf_gv11b.h"
u32 gv11b_get_sema_wait_cmd_size(void)
{
return 10U;
}
u32 gv11b_get_sema_incr_cmd_size(void)
{
return 12U;
}
void gv11b_add_sema_cmd(struct gk20a *g,
struct nvgpu_semaphore *s, u64 sema_va,
struct priv_cmd_entry *cmd,
u32 off, bool acquire, bool wfi)
{
nvgpu_log_fn(g, " ");
/* sema_addr_lo */
nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010017);
nvgpu_mem_wr32(g, cmd->mem, off++, sema_va & 0xffffffffULL);
/* sema_addr_hi */
nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010018);
nvgpu_mem_wr32(g, cmd->mem, off++, (sema_va >> 32ULL) & 0xffULL);
/* payload_lo */
nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010019);
nvgpu_mem_wr32(g, cmd->mem, off++, nvgpu_semaphore_get_value(s));
/* payload_hi : ignored */
nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001a);
nvgpu_mem_wr32(g, cmd->mem, off++, 0);
if (acquire) {
/* sema_execute : acq_strict_geq | switch_en | 32bit */
nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001b);
nvgpu_mem_wr32(g, cmd->mem, off++, U32(0x2) | BIT32(12));
} else {
/* sema_execute : release | wfi | 32bit */
nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001b);
nvgpu_mem_wr32(g, cmd->mem, off++,
U32(0x1) | ((wfi ? U32(0x1) : U32(0x0)) << 20U));
/* non_stall_int : payload is ignored */
nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010008);
nvgpu_mem_wr32(g, cmd->mem, off++, 0);
}
}

38
drivers/gpu/nvgpu/common/sync/sema_cmdbuf_gv11b.h Normal file
View File

@@ -0,0 +1,38 @@
/*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_SYNC_SEMA_CMDBUF_GV11B_H
#define NVGPU_SYNC_SEMA_CMDBUF_GV11B_H
#include <nvgpu/types.h>
struct gk20a;
struct priv_cmd_entry;
struct nvgpu_semaphore;
u32 gv11b_get_sema_wait_cmd_size(void);
u32 gv11b_get_sema_incr_cmd_size(void);
void gv11b_add_sema_cmd(struct gk20a *g,
struct nvgpu_semaphore *s, u64 sema_va,
struct priv_cmd_entry *cmd,
u32 off, bool acquire, bool wfi);
#endif /* NVGPU_SYNC_SEMA_CMDBUF_GV11B_H */

7
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -72,6 +72,7 @@
#include "common/nvlink/nvlink_tu104.h"
#include "common/pmu/perf/perf_gv100.h"
#include "common/sync/syncpt_cmdbuf_gv11b.h"
#include "common/sync/sema_cmdbuf_gv11b.h"
#include "common/regops/regops_gv100.h"
#include "common/fifo/runlist_gk20a.h"
#include "common/fifo/runlist_gv11b.h"
@@ -776,9 +777,9 @@ static const struct gpu_ops gv100_ops = {
gv11b_get_syncpt_incr_per_release,
.get_sync_ro_map = gv11b_get_sync_ro_map,
#endif
.get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size,
.get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size,
.add_sema_cmd = gv11b_fifo_add_sema_cmd,
.get_sema_wait_cmd_size = gv11b_get_sema_wait_cmd_size,
.get_sema_incr_cmd_size = gv11b_get_sema_incr_cmd_size,
.add_sema_cmd = gv11b_add_sema_cmd,
},
.runlist = {
.update_runlist = gk20a_fifo_update_runlist,

49
drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
View File

@@ -1881,55 +1881,6 @@ void gv11b_fifo_deinit_eng_method_buffers(struct gk20a *g,
nvgpu_log_info(g, "eng method buffers de-allocated");
}
u32 gv11b_fifo_get_sema_wait_cmd_size(void)
{
return 10;
}
u32 gv11b_fifo_get_sema_incr_cmd_size(void)
{
return 12;
}
void gv11b_fifo_add_sema_cmd(struct gk20a *g,
struct nvgpu_semaphore *s, u64 sema_va,
struct priv_cmd_entry *cmd,
u32 off, bool acquire, bool wfi)
{
nvgpu_log_fn(g, " ");
/* sema_addr_lo */
nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010017);
nvgpu_mem_wr32(g, cmd->mem, off++, sema_va & 0xffffffffULL);
/* sema_addr_hi */
nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010018);
nvgpu_mem_wr32(g, cmd->mem, off++, (sema_va >> 32ULL) & 0xffULL);
/* payload_lo */
nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010019);
nvgpu_mem_wr32(g, cmd->mem, off++, nvgpu_semaphore_get_value(s));
/* payload_hi : ignored */
nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001a);
nvgpu_mem_wr32(g, cmd->mem, off++, 0);
if (acquire) {
/* sema_execute : acq_strict_geq | switch_en | 32bit */
nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001b);
nvgpu_mem_wr32(g, cmd->mem, off++, U32(0x2) | BIT32(12));
} else {
/* sema_execute : release | wfi | 32bit */
nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001b);
nvgpu_mem_wr32(g, cmd->mem, off++,
U32(0x1) | ((wfi ? U32(0x1) : U32(0x0)) << 20U));
/* non_stall_int : payload is ignored */
nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010008);
nvgpu_mem_wr32(g, cmd->mem, off++, 0);
}
}
int gv11b_init_fifo_setup_hw(struct gk20a *g)
{
struct fifo_gk20a *f = &g->fifo;

6
drivers/gpu/nvgpu/gv11b/fifo_gv11b.h
View File

@@ -100,12 +100,6 @@ void gv11b_fifo_init_eng_method_buffers(struct gk20a *g,
struct tsg_gk20a *tsg);
void gv11b_fifo_deinit_eng_method_buffers(struct gk20a *g,
struct tsg_gk20a *tsg);
u32 gv11b_fifo_get_sema_wait_cmd_size(void);
u32 gv11b_fifo_get_sema_incr_cmd_size(void);
void gv11b_fifo_add_sema_cmd(struct gk20a *g,
struct nvgpu_semaphore *s, u64 sema_va,
struct priv_cmd_entry *cmd,
u32 off, bool acquire, bool wfi);
int gv11b_init_fifo_setup_hw(struct gk20a *g);
void gv11b_fifo_tsg_verify_status_faulted(struct channel_gk20a *ch);

7
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -63,6 +63,7 @@
#include "common/top/top_gm20b.h"
#include "common/top/top_gp10b.h"
#include "common/sync/syncpt_cmdbuf_gv11b.h"
#include "common/sync/sema_cmdbuf_gv11b.h"
#include "common/regops/regops_gv11b.h"
#include "common/fifo/runlist_gk20a.h"
#include "common/fifo/runlist_gv11b.h"
@@ -729,9 +730,9 @@ static const struct gpu_ops gv11b_ops = {
gv11b_get_syncpt_incr_per_release,
.get_sync_ro_map = gv11b_get_sync_ro_map,
#endif
.get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size,
.get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size,
.add_sema_cmd = gv11b_fifo_add_sema_cmd,
.get_sema_wait_cmd_size = gv11b_get_sema_wait_cmd_size,
.get_sema_incr_cmd_size = gv11b_get_sema_incr_cmd_size,
.add_sema_cmd = gv11b_add_sema_cmd,
},
.runlist = {
.reschedule_runlist = gv11b_fifo_reschedule_runlist,

7
drivers/gpu/nvgpu/tu104/hal_tu104.c
View File

@@ -77,6 +77,7 @@
#include "common/nvlink/nvlink_gv100.h"
#include "common/nvlink/nvlink_tu104.h"
#include "common/sync/syncpt_cmdbuf_gv11b.h"
#include "common/sync/sema_cmdbuf_gv11b.h"
#include "common/regops/regops_tu104.h"
#include "common/fifo/runlist_gk20a.h"
#include "common/fifo/runlist_gv11b.h"
@@ -806,9 +807,9 @@ static const struct gpu_ops tu104_ops = {
gv11b_get_syncpt_incr_per_release,
.get_sync_ro_map = gv11b_get_sync_ro_map,
#endif
.get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size,
.get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size,
.add_sema_cmd = gv11b_fifo_add_sema_cmd,
.get_sema_wait_cmd_size = gv11b_get_sema_wait_cmd_size,
.get_sema_incr_cmd_size = gv11b_get_sema_incr_cmd_size,
.add_sema_cmd = gv11b_add_sema_cmd,
},
.runlist = {
.update_runlist = gk20a_fifo_update_runlist,

7
drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -41,6 +41,7 @@
#include "common/fuse/fuse_gm20b.h"
#include "common/fuse/fuse_gp10b.h"
#include "common/sync/syncpt_cmdbuf_gv11b.h"
#include "common/sync/sema_cmdbuf_gv11b.h"
#include "common/regops/regops_gv11b.h"
#include "common/fifo/runlist_gv11b.h"
@@ -498,9 +499,9 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.get_syncpt_incr_cmd_size = gv11b_get_syncpt_incr_cmd_size,
.get_sync_ro_map = vgpu_gv11b_fifo_get_sync_ro_map,
#endif
.get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size,
.get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size,
.add_sema_cmd = gv11b_fifo_add_sema_cmd,
.get_sema_wait_cmd_size = gv11b_get_sema_wait_cmd_size,
.get_sema_incr_cmd_size = gv11b_get_sema_incr_cmd_size,
.add_sema_cmd = gv11b_add_sema_cmd,
},
.runlist = {
.reschedule_runlist = NULL,