Alex Waterman c8da754643 gpu: nvgpu: Clear FIFO intr before processing finished jobs ...

Clear the FIFO interrupt before prcessing the job list after
receiving a nonstalling interrupt. This prevents a race in which
some non-stalling interrupts after a semaphore incr can get lost.

Bug 1732449
JIRA DNVGPU-12

Change-Id: I03df56b2ebca4ed8a0aeb26dd5480c91ffb42d8b
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1133791
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

2016-04-29 14:46:55 -07:00

drivers/gpu/nvgpu

gpu: nvgpu: Clear FIFO intr before processing finished jobs

2016-04-29 14:46:55 -07:00

include

gpu: nvgpu: add TSG timeslice support

2016-04-27 08:47:22 -07:00

scripts

checkpatch: add checkpatch.pl

2016-04-19 09:23:35 -07:00

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42 MiB