Vedashree Vidwans caf2b991cd gpu: nvgpu: fix MISRA 10.1 and 10.4 in log macro
Rule 10.x necessitates operands to have essential type; left and right
operands should be of same width and type.
This patch updates NVGPU_DEFAULT_DBG_MASK to be u32.

Jira NVGPU-4075

Change-Id: I3af250d27bb629a6c531dd6843bc6dbcb9a1cca5
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2224778
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2020-12-15 14:10:29 -06:00
Description
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42 MiB