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Moved following structure defs from gr_gk20a.h to gr_falcon_priv.h: gk20a_ctxsw_bootloader_desc -> nvgpu_ctxsw_bootloader_desc fecs_method_op_gk20a -> nvgpu_fecs_method_op Updated code to use these new structure defs. JIRA NVGPU-1881 Change-Id: Ie0f06ce6f2bfeb1b4ec4b01643c206bd863a7a88 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2089317 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
59 lines
1.5 KiB
C
59 lines
1.5 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef GR_FALCON_PRIV_H
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#define GR_FALOCN_PRIV_H
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#include <nvgpu/types.h>
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struct nvgpu_fecs_method_op {
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struct {
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u32 addr;
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u32 data;
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} method;
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struct {
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u32 id;
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u32 data;
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u32 clr;
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u32 *ret;
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u32 ok;
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u32 fail;
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} mailbox;
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struct {
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u32 ok;
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u32 fail;
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} cond;
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};
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struct nvgpu_ctxsw_bootloader_desc {
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u32 start_offset;
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u32 size;
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u32 imem_offset;
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u32 entry_point;
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};
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#endif /* GR_FALOCN_PRIV_H */
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