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5614a51dcc
MISRA Rule-17.7 requires the return value of all functions to be used. Fix is either to use the return value or change the function to return void. In the case of the pmu_setup_elpg operation, all implementations were always returning 0, so this patch changes the signature to return void instead. JIRA NVGPU-3036 Change-Id: I6f0a79314535ba9e3c65d28399b117b058bb23ca Signed-off-by: Nicolas Benech <nbenech@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2092680 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
247 lines
7.5 KiB
C
247 lines
7.5 KiB
C
/*
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* GM20B PMU
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*
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* Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/timers.h>
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#include <nvgpu/pmu.h>
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#include <nvgpu/mm.h>
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#include <nvgpu/fuse.h>
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#include <nvgpu/enabled.h>
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#include <nvgpu/io.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/bug.h>
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#include <nvgpu/pmu/cmd.h>
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#include "pmu_gk20a.h"
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#include "pmu_gm20b.h"
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#include <nvgpu/hw/gm20b/hw_pwr_gm20b.h>
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/* PROD settings for ELPG sequencing registers*/
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static struct pg_init_sequence_list _pginitseq_gm20b[] = {
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{ 0x0010ab10U, 0x8180U},
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{ 0x0010e118U, 0x83828180U},
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{ 0x0010e068U, 0x0U},
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{ 0x0010e06cU, 0x00000080U},
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{ 0x0010e06cU, 0x00000081U},
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{ 0x0010e06cU, 0x00000082U},
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{ 0x0010e06cU, 0x00000083U},
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{ 0x0010e06cU, 0x00000084U},
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{ 0x0010e06cU, 0x00000085U},
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{ 0x0010e06cU, 0x00000086U},
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{ 0x0010e06cU, 0x00000087U},
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{ 0x0010e06cU, 0x00000088U},
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{ 0x0010e06cU, 0x00000089U},
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{ 0x0010e06cU, 0x0000008aU},
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{ 0x0010e06cU, 0x0000008bU},
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{ 0x0010e06cU, 0x0000008cU},
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{ 0x0010e06cU, 0x0000008dU},
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{ 0x0010e06cU, 0x0000008eU},
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{ 0x0010e06cU, 0x0000008fU},
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{ 0x0010e06cU, 0x00000090U},
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{ 0x0010e06cU, 0x00000091U},
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{ 0x0010e06cU, 0x00000092U},
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{ 0x0010e06cU, 0x00000093U},
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{ 0x0010e06cU, 0x00000094U},
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{ 0x0010e06cU, 0x00000095U},
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{ 0x0010e06cU, 0x00000096U},
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{ 0x0010e06cU, 0x00000097U},
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{ 0x0010e06cU, 0x00000098U},
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{ 0x0010e06cU, 0x00000099U},
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{ 0x0010e06cU, 0x0000009aU},
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{ 0x0010e06cU, 0x0000009bU},
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{ 0x0010ab14U, 0x00000000U},
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{ 0x0010ab18U, 0x00000000U},
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{ 0x0010e024U, 0x00000000U},
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{ 0x0010e028U, 0x00000000U},
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{ 0x0010e11cU, 0x00000000U},
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{ 0x0010e120U, 0x00000000U},
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{ 0x0010ab1cU, 0x02010155U},
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{ 0x0010e020U, 0x001b1b55U},
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{ 0x0010e124U, 0x01030355U},
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{ 0x0010ab20U, 0x89abcdefU},
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{ 0x0010ab24U, 0x00000000U},
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{ 0x0010e02cU, 0x89abcdefU},
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{ 0x0010e030U, 0x00000000U},
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{ 0x0010e128U, 0x89abcdefU},
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{ 0x0010e12cU, 0x00000000U},
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{ 0x0010ab28U, 0x74444444U},
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{ 0x0010ab2cU, 0x70000000U},
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{ 0x0010e034U, 0x74444444U},
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{ 0x0010e038U, 0x70000000U},
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{ 0x0010e130U, 0x74444444U},
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{ 0x0010e134U, 0x70000000U},
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{ 0x0010ab30U, 0x00000000U},
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{ 0x0010ab34U, 0x00000001U},
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{ 0x00020004U, 0x00000000U},
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{ 0x0010e138U, 0x00000000U},
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{ 0x0010e040U, 0x00000000U},
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};
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void gm20b_pmu_setup_elpg(struct gk20a *g)
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{
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size_t reg_writes;
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size_t index;
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nvgpu_log_fn(g, " ");
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if (g->can_elpg && g->elpg_enabled) {
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reg_writes = ARRAY_SIZE(_pginitseq_gm20b);
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/* Initialize registers with production values*/
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for (index = 0; index < reg_writes; index++) {
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gk20a_writel(g, _pginitseq_gm20b[index].regaddr,
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_pginitseq_gm20b[index].writeval);
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}
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}
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nvgpu_log_fn(g, "done");
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}
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void gm20b_write_dmatrfbase(struct gk20a *g, u32 addr)
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{
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gk20a_writel(g, pwr_falcon_dmatrfbase_r(), addr);
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}
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/*Dump Security related fuses*/
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void pmu_dump_security_fuses_gm20b(struct gk20a *g)
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{
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u32 val = 0;
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nvgpu_err(g, "FUSE_OPT_SEC_DEBUG_EN_0: 0x%x",
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g->ops.fuse.fuse_opt_sec_debug_en(g));
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nvgpu_err(g, "FUSE_OPT_PRIV_SEC_EN_0: 0x%x",
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g->ops.fuse.fuse_opt_priv_sec_en(g));
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if (g->ops.fuse.read_gcplex_config_fuse(g, &val) != 0) {
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nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0: 0x%x", val);
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}
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}
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bool gm20b_pmu_is_debug_mode_en(struct gk20a *g)
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{
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u32 ctl_stat = gk20a_readl(g, pwr_pmu_scpctl_stat_r());
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return pwr_pmu_scpctl_stat_debug_mode_v(ctl_stat) != 0U;
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}
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int gm20b_ns_pmu_setup_hw_and_bootstrap(struct gk20a *g)
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{
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struct nvgpu_pmu *pmu = &g->pmu;
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nvgpu_log_fn(g, " ");
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nvgpu_mutex_acquire(&pmu->isr_mutex);
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nvgpu_falcon_reset(&pmu->flcn);
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pmu->isr_enabled = true;
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nvgpu_mutex_release(&pmu->isr_mutex);
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/* setup apertures - virtual */
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gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
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pwr_fbif_transcfg_mem_type_virtual_f());
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gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
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pwr_fbif_transcfg_mem_type_virtual_f());
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/* setup apertures - physical */
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gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
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pwr_fbif_transcfg_mem_type_physical_f() |
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pwr_fbif_transcfg_target_local_fb_f());
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gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
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pwr_fbif_transcfg_mem_type_physical_f() |
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pwr_fbif_transcfg_target_coherent_sysmem_f());
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gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
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pwr_fbif_transcfg_mem_type_physical_f() |
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pwr_fbif_transcfg_target_noncoherent_sysmem_f());
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return g->ops.pmu.pmu_nsbootstrap(pmu);
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}
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void gm20b_pmu_setup_apertures(struct gk20a *g)
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{
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/* setup apertures - virtual */
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gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
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pwr_fbif_transcfg_mem_type_physical_f() |
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pwr_fbif_transcfg_target_local_fb_f());
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gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
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pwr_fbif_transcfg_mem_type_virtual_f());
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/* setup apertures - physical */
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gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
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pwr_fbif_transcfg_mem_type_physical_f() |
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pwr_fbif_transcfg_target_local_fb_f());
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gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
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pwr_fbif_transcfg_mem_type_physical_f() |
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pwr_fbif_transcfg_target_coherent_sysmem_f());
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gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
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pwr_fbif_transcfg_mem_type_physical_f() |
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pwr_fbif_transcfg_target_noncoherent_sysmem_f());
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}
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void gm20b_pmu_flcn_setup_boot_config(struct gk20a *g)
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{
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struct mm_gk20a *mm = &g->mm;
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u32 inst_block_ptr;
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nvgpu_log_fn(g, " ");
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/* setup apertures */
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if (g->ops.pmu.setup_apertures != NULL) {
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g->ops.pmu.setup_apertures(g);
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}
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/* Clearing mailbox register used to reflect capabilities */
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gk20a_writel(g, pwr_falcon_mailbox1_r(), 0);
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/* enable the context interface */
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gk20a_writel(g, pwr_falcon_itfen_r(),
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gk20a_readl(g, pwr_falcon_itfen_r()) |
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pwr_falcon_itfen_ctxen_enable_f());
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/*
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* The instance block address to write is the lower 32-bits of the 4K-
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* aligned physical instance block address.
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*/
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inst_block_ptr = nvgpu_inst_block_ptr(g, &mm->pmu.inst_block);
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gk20a_writel(g, pwr_pmu_new_instblk_r(),
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pwr_pmu_new_instblk_ptr_f(inst_block_ptr) |
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pwr_pmu_new_instblk_valid_f(1U) |
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(nvgpu_is_enabled(g, NVGPU_USE_COHERENT_SYSMEM) ?
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pwr_pmu_new_instblk_target_sys_coh_f() :
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pwr_pmu_new_instblk_target_sys_ncoh_f())) ;
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}
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void gm20b_secured_pmu_start(struct gk20a *g)
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{
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gk20a_writel(g, pwr_falcon_cpuctl_alias_r(),
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pwr_falcon_cpuctl_startcpu_f(1));
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}
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bool gm20b_is_pmu_supported(struct gk20a *g)
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{
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return true;
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}
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void gm20b_clear_pmu_bar0_host_err_status(struct gk20a *g)
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{
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u32 status;
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status = gk20a_readl(g, pwr_pmu_bar0_host_error_r());
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gk20a_writel(g, pwr_pmu_bar0_host_error_r(), status);
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}
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