mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-23 18:16:01 +03:00
b4ec1c5dff
Renamed and moved from fifo to channel gk20a_debug_dump_all_channel_status_ramfc -> nvgpu_channel_debug_dump_all gk20a_dump_channel_status_ramfc -> gk20a_channel_debug_dump gv11b_dump_channel_status_ramfc -> gv11b_channel_debug_dump Moved nvgpu_channel_dump_info struct to channel.h Moved nvgpu_channel_hw_state struct to channel.h Moved dump_channel_status_ramfc fifo ops to channel ops as debug_dump JIRA NVGPU-2978 Change-Id: I696e5029d9e6ca4dc3516651b4d4f5230fe8b0b0 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2092709 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
51 lines
1.9 KiB
C
51 lines
1.9 KiB
C
/*
|
|
* fifo common definitions (gr host)
|
|
*
|
|
* Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved.
|
|
*
|
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
* copy of this software and associated documentation files (the "Software"),
|
|
* to deal in the Software without restriction, including without limitation
|
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
* and/or sell copies of the Software, and to permit persons to whom the
|
|
* Software is furnished to do so, subject to the following conditions:
|
|
*
|
|
* The above copyright notice and this permission notice shall be included in
|
|
* all copies or substantial portions of the Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
|
* DEALINGS IN THE SOFTWARE.
|
|
*/
|
|
|
|
#ifndef NVGPU_FIFO_COMMON_H
|
|
#define NVGPU_FIFO_COMMON_H
|
|
|
|
#define RC_TYPE_NO_RC 0U
|
|
#define RC_TYPE_MMU_FAULT 1U
|
|
#define RC_TYPE_PBDMA_FAULT 2U
|
|
#define RC_TYPE_GR_FAULT 3U
|
|
#define RC_TYPE_PREEMPT_TIMEOUT 4U
|
|
#define RC_TYPE_CTXSW_TIMEOUT 5U
|
|
#define RC_TYPE_RUNLIST_UPDATE_TIMEOUT 6U
|
|
#define RC_TYPE_FORCE_RESET 7U
|
|
#define RC_TYPE_SCHED_ERR 8U
|
|
|
|
#define INVAL_ID (~U32(0U))
|
|
|
|
#define CTXSW_TIMEOUT_PERIOD_MS 100U
|
|
|
|
struct gk20a;
|
|
|
|
int nvgpu_fifo_init_support(struct gk20a *g);
|
|
int nvgpu_fifo_setup_sw(struct gk20a *g);
|
|
int nvgpu_fifo_setup_sw_common(struct gk20a *g);
|
|
void nvgpu_fifo_cleanup_sw(struct gk20a *g);
|
|
void nvgpu_fifo_cleanup_sw_common(struct gk20a *g);
|
|
|
|
#endif /* NVGPU_FIFO_COMMON_H */
|