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476f44a0a4
lpwr_entry_idx member is required to map pstate with lwpr tables JIRA DNVGPU-71 Change-Id: I4cad54c61dec7ad7e3c1a60178938d0eeaf65e24 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1247303 (cherry-picked from commit b1f6e0036922d2104b3d08548219e72a38f2e231) Reviewed-on: http://git-master/r/1267403 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
60 lines
1.4 KiB
C
60 lines
1.4 KiB
C
/*
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* general p state infrastructure
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*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef __PSTATE_H__
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#define __PSTATE_H__
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#include "gk20a/gk20a.h"
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#include "clk/clk.h"
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#define CTRL_PERF_PSTATE_TYPE_3X 0x3
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#define CTRL_PERF_PSTATE_P0 0
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#define CTRL_PERF_PSTATE_P5 5
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#define CTRL_PERF_PSTATE_P8 8
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#define CLK_SET_INFO_MAX_SIZE (32)
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struct clk_set_info {
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enum nv_pmu_clk_clkwhich clkwhich;
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u32 nominal_mhz;
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u32 min_mhz;
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u32 max_mhz;
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};
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struct clk_set_info_list {
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u32 num_info;
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struct clk_set_info clksetinfo[CLK_SET_INFO_MAX_SIZE];
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};
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struct pstate {
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struct boardobj super;
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u32 num;
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u8 lpwr_entry_idx;
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struct clk_set_info_list clklist;
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};
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struct pstates {
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struct boardobjgrp_e32 super;
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u32 num_levels;
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};
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int gk20a_init_pstate_support(struct gk20a *g);
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int gk20a_init_pstate_pmu_support(struct gk20a *g);
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struct clk_set_info *pstate_get_clk_set_info(struct gk20a *g, u32 pstate_num,
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enum nv_pmu_clk_clkwhich clkwhich);
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#endif /* __PSTATE_H__ */
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