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935c5f6578
This patch addresses misra violations due to SDL error reporting callbacks. In particular, it addresses the following misra violation: - misra_c_2012_directive_4_7_violation: Calling function "nvgpu_report_*_err()" which returns error information without testing the error information. JIRA NVGPU-4025 Change-Id: Ia10b6b3fd9c127a8c5189c3b6ba316f243cedf04 Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2196895 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
88 lines
2.6 KiB
C
88 lines
2.6 KiB
C
/*
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* Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/runlist.h>
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#include <nvgpu/types.h>
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#include <nvgpu/channel.h>
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#include <nvgpu/tsg.h>
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#include <nvgpu/preempt.h>
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#include <nvgpu/nvgpu_err.h>
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u32 nvgpu_preempt_get_timeout(struct gk20a *g)
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{
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return g->ctxsw_timeout_period_ms;
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}
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int nvgpu_preempt_channel(struct gk20a *g, struct nvgpu_channel *ch)
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{
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int err;
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struct nvgpu_tsg *tsg = nvgpu_tsg_from_ch(ch);
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if (tsg != NULL) {
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err = g->ops.fifo.preempt_tsg(ch->g, tsg);
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} else {
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err = g->ops.fifo.preempt_channel(ch->g, ch);
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}
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return err;
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}
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/* called from rc */
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void nvgpu_preempt_poll_tsg_on_pbdma(struct gk20a *g,
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struct nvgpu_tsg *tsg)
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{
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struct nvgpu_fifo *f = &g->fifo;
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u32 runlist_id;
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unsigned long runlist_served_pbdmas;
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unsigned long pbdma_id_bit;
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u32 tsgid, pbdma_id;
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if (g->ops.fifo.preempt_poll_pbdma == NULL) {
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return;
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}
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if (tsg == NULL) {
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return;
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}
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tsgid = tsg->tsgid;
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runlist_id = tsg->runlist_id;
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runlist_served_pbdmas = f->runlist_info[runlist_id]->pbdma_bitmask;
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for_each_set_bit(pbdma_id_bit, &runlist_served_pbdmas, f->num_pbdma) {
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pbdma_id = U32(pbdma_id_bit);
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/*
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* If pbdma preempt fails the only option is to reset
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* GPU. Any sort of hang indicates the entire GPU’s
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* memory system would be blocked.
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*/
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if (g->ops.fifo.preempt_poll_pbdma(g, tsgid, pbdma_id) != 0) {
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nvgpu_report_host_err(g, NVGPU_ERR_MODULE_HOST,
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pbdma_id,
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GPU_HOST_PBDMA_PREEMPT_ERROR, 0);
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nvgpu_err(g, "PBDMA preempt failed");
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}
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}
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}
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