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e424e4791a
-Renamed and moved nvgpu_pmu_perf struct from public to unit specific -Renamed all functions as per public/private format NVGPU-5029 Change-Id: If3f479bb1443850a5c8a8714cd1c9da346cb566a Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2300609 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
75 lines
2.4 KiB
C
75 lines
2.4 KiB
C
/*
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* general perf structures & definitions
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*
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* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef PMU_PERF_H_
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#define PMU_PERF_H_
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#include "vfe_equ.h"
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#include "vfe_var.h"
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#include "change_seq.h"
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#include "pstate.h"
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/* PERF RPC ID Definitions */
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#define NV_PMU_RPC_ID_PERF_VFE_CALLBACK 0x01U
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#define NV_PMU_RPC_ID_PERF_SEQ_COMPLETION 0x02U
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#define NV_PMU_RPC_ID_PERF_PSTATES_INVALIDATE 0x03U
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/*
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* Defines the structure that holds data
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* used to execute LOAD RPC.
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*/
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struct nv_pmu_rpc_struct_perf_load {
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/* [IN/OUT] Must be first field in RPC structure */
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struct nv_pmu_rpc_header hdr;
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bool b_load;
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u32 scratch[1];
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};
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/*
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* Simply a union of all specific PERF messages. Forms the general packet
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* exchanged between the Kernel and PMU when sending and receiving PERF messages
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* (respectively).
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*/
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struct pmu_nvgpu_rpc_perf_event {
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struct pmu_hdr msg_hdr;
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struct pmu_nvgpu_rpc_header rpc_hdr;
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};
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struct perf_vfe_invalidate {
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bool state_change;
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struct nvgpu_cond wq;
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struct nvgpu_thread state_task;
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};
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struct nvgpu_pmu_perf {
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struct vfe_vars vfe_varobjs;
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struct vfe_equs vfe_equobjs;
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struct pstates pstatesobjs;
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struct perf_vfe_invalidate vfe_init;
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struct change_seq_pmu changeseq_pmu;
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};
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#endif /* PMU_PERF_H_ */
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