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3bfab5df3f
Below CE interrupts are disabled on safety build as fault and switch mechanism is not supported on safety: NV_CE_LCE_INTR_STATUS_MTHD_BUFFER_FAULT NV_CE_LCE_INTR_STATUS_FBUF_CRC_FAIL NV_CE_LCE_INTR_STATUS_FBUF_MAGIC_CHK_FAIL Bug 3548082 Change-Id: I400cd02a8c9888b7ef0d71bbc1f7d792b48e8227 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2679052 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
54 lines
1.9 KiB
C
54 lines
1.9 KiB
C
/*
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* Pascal GPU series Copy Engine.
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*
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* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/io.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/mc.h>
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#include <nvgpu/cic_mon.h>
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#include <nvgpu/nvgpu_err.h>
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#include "ce_gp10b.h"
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#include <nvgpu/hw/gp10b/hw_ce_gp10b.h>
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u32 gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
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{
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u32 nonstall_ops = 0U;
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u32 ce_intr = nvgpu_readl(g, ce_intr_status_r(inst_id));
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(void)pri_base;
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nvgpu_log(g, gpu_dbg_intr, "ce nonstall isr %08x %08x",
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ce_intr, inst_id);
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if ((ce_intr & ce_intr_status_nonblockpipe_pending_f()) != 0U) {
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nvgpu_writel(g, ce_intr_status_r(inst_id),
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ce_intr_status_nonblockpipe_pending_f());
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nonstall_ops |= (NVGPU_CIC_NONSTALL_OPS_WAKEUP_SEMAPHORE |
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NVGPU_CIC_NONSTALL_OPS_POST_EVENTS);
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}
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return nonstall_ops;
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}
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