mirror of
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Change NV license for nvsched sources and Makefile.doxygen to MIT
license as those can be distributed with other linux sources but
they are also used in qnx.
Bug 3871403
Change-Id: Iefc957b4afdf4c3c2ff19df144caac9790490114
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2814847
(cherry picked from commit 406e5392b7)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2818121
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
353 lines
12 KiB
C++
353 lines
12 KiB
C++
/*
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* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVS_CONTROL_INTERFACE_H
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#define NVS_CONTROL_INTERFACE_H
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/**
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* @file
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* @brief <b>NVIDIA GPU domain scheduler asynchronous messaging interface</b>
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*/
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#include "nvs-control-messages.h"
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#if defined(__cplusplus)
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#include <cstdint>
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#elif !defined(__KERNEL__)
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#include <stdint.h>
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#endif
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/**
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* @brief Value for nvs_domain_msg_fifo_control::get to indicate disabled
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* flow control.
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*
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* @since 1.0.0
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*/
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#define NVS_DOMAIN_MSG_FIFO_CONTROL_GET_FLOW_CTRL_DISABLED (0xFFFFFFFFU)
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/**
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* @brief Least significant bit of field PUT in nvs_domain_msg_fifo_control::put_revolutions
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*/
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#define NVS_DOMAIN_MSG_FIFO_CONTROL_PUT_REVOLUTIONS_PUT_LSB (0U)
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/**
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* @brief Most significant bit of field PUT in nvs_domain_msg_fifo_control::put_revolutions
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*/
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#define NVS_DOMAIN_MSG_FIFO_CONTROL_PUT_REVOLUTIONS_PUT_MSB (31U)
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/**
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* @brief Least significant bit of field REVOLUTIONS in nvs_domain_msg_fifo_control::put_revolutions
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*/
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#define NVS_DOMAIN_MSG_FIFO_CONTROL_PUT_REVOLUTIONS_REVOLUTIONS_LSB (32U)
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/**
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* @brief Most significant bit of field REVOLUTIONS in nvs_domain_msg_fifo_control::put_revolutions
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*/
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#define NVS_DOMAIN_MSG_FIFO_CONTROL_PUT_REVOLUTIONS_REVOLUTIONS_MSB (63U)
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/**
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* @brief The FIFO ring buffer control block
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*
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* FIFO ring buffer initialization
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* -------------------------------
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*
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* The FIFO ring buffer control block should be initialized on allocation as
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* follows:
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* - client --> scheduler:
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* - all zeroes
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* - scheduler --> client:
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* - nvs_domain_msg_fifo_control::get =
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* #NVS_DOMAIN_MSG_FIFO_CONTROL_GET_FLOW_CTRL_DISABLED.
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* - everything else zeroes
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*
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* The FIFO size in entries is calculated as follows from the buffer size:
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*
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* @code
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* num_messages = (buffer_size - sizeof(nvs_domain_msg_fifo_control)) / sizeof(nvs_domain_message)
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* @endcode
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*
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* With the current data structure layouts, this formula with sizeof substitutions is as:
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*
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* @code
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* num_messages = (buffer_size - 128U) / 64U
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* @endcode
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*
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* For example, the number of messages in the FIFO is 1022 for a buffer of size 64K.
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*
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*
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* Adding a message in the FIFO ring buffer
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* ----------------------------------------
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*
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* The sender is suggested to maintain the following variables locally:
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* - @c local_put --- local copy of put index
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* - @c local_revolution_count --- local copy of revolution count
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* - @c local_num_dropped_messages --- local copy of number of dropped messages
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* - @c local_fifo_size_entries --- local copy of the FIFO ring buffer size
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*
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* When the sender is initialized, the local variables should be initialized
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* from the fields in #nvs_domain_msg_fifo_control, except for the FIFO size. The
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* FIFO size is received from nvgpu-rm as part of the physical buffer
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* parameters.
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*
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* The sequence for adding a message in the FIFO ring buffer is as follows:
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*
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* 1. Read nvs_domain_msg_fifo_control::get as @c get
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* 2. Determine whether there is space for the message. There are two cases:
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* - @c get == #NVS_DOMAIN_MSG_FIFO_CONTROL_GET_FLOW_CTRL_DISABLED: flow control disabled, space always available
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* - otherwise: space is available when
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* <tt>((local_put + 1) % local_fifo_size_entries) != get</tt>
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* 3. If out of space, then:
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* - increment @c local_num_dropped_messages
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* - write it to nvs_domain_msg_fifo_control::num_dropped_messages
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* - do not proceed with this sequence
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* - Notes:
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* - scheduler --> client: nvs_domain_msg_fifo_control::num_dropped_messages
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* indicates that messages were dropped. Logging an
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* overflow event may be applicable.
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* - client --> scheduler: The usermode client should return an error.
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* 4. Read-write memory barrier
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* 5. Write the message to nvs_domain_msg_fifo::messages[local_put]
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* - NOTE: if the message size is less than the size of the array entry, it
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* should be appended with 0 to fill the entry. This allows extending the
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* messages with new fields in later protocol versions in a backwards
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* compatible manner.
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* - NOTE: this update does not need to be atomic
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* 6. Write memory barrier
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* 7. Increment @c local_put (modulo fifo size). In case of a wrap-around,
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* increment also @c local_revolution_count
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* 8. Write <tt>local_put | (local_revolution_count << 32)</tt>
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* to nvs_domain_msg_fifo_control::put_revolutions. This write
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* should be atomic 64-bit write.
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*
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*
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* Receiving a message in the FIFO ring buffer (read-write access client)
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* ---------------------------------------------------------------
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*
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* The receiver is suggested to maintain the following variables locally:
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* - @c local_get --- local copy of get index
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* - @c local_fifo_size_entries --- local copy of the FIFO ring buffer size
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*
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* When the reader is initialized, it should:
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*
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* 1. atomic read nvs_domain_msg_fifo_control::put_revolutions and store the
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* 32-bit lower bits as @c local_get
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* 2. store @c local_get to nvs_domain_msg_fifo_control::get. This enables
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* flow control.
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*
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* When the reader exits, it should write
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* #NVS_DOMAIN_MSG_FIFO_CONTROL_GET_FLOW_CTRL_DISABLED in
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* nvs_domain_msg_fifo_control::get. This disables flow control. Further,
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* nvgpu-rm should also write
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* #NVS_DOMAIN_MSG_FIFO_CONTROL_GET_FLOW_CTRL_DISABLED in
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* nvs_domain_msg_fifo_control::get when the R/W reader client exits. This
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* is to ensure that abnormal client exit (e.g., process crash) disables flow
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* control.
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*
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* The sequence for reading a message:
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*
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* 1. Atomic read the bottom 32 bits (or whole field) of
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* nvs_domain_msg_fifo_control::put_revolutions as @c put
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* 2. If local_get == put, there are no more messages. Exit this
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* sequence.
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* 3. Read memory barrier
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* 4. Read the message from nvs_domain_msg_fifo::messages[local_get]
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* (non-atomic read ok)
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* 5. Read-write memory barrier
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* 6. Increment local_get (mod FIFO size)
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* 7. Atomic write nvs_domain_msg_fifo_control::get
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*
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*
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* Receiving a message in the FIFO ring buffer (read-only access client)
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* ---------------------------------------------------------------
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*
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* <b>NOTE:</b> The read-only reader client should not be used for
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* safety-critical operation. It does not have flow control and it is subject to
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* FIFO overruns. The read-only client is intended for diagnostics and tracing.
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*
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* The receiver is suggested to maintain the following variables locally:
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* - @c local_get --- local copy of get index
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* - @c local_revolutions --- local copy of FIFO revolutions
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* - @c local_fifo_size_entries --- local copy of the FIFO ring buffer size
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*
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* When the reader is initialized, it should:
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*
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* 1. atomic read nvs_domain_msg_fifo_control::put_revolutions and store the
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* lower 32 bits as @c local_get, and the upper 32 bits as @c
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* local_revolutions
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*
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* The sequence for reading a message:
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*
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* 1. Atomic read nvs_domain_msg_fifo_control::put_revolutions as @c put and
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* @c revolutions
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* 2. Determine whether the reader is more than a full revolution behind the
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* writer. One way to do this is to calculate the total number of messages
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* read and written, and then calculate the cyclic difference of the
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* totals.
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* @code
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* cycleSize = FIFO_entries * (1 << 32) ; num messages until 'revolutions' wraps around
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* messagesRead = local_get + (local_revolutions * FIFO_entries)
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* messagesWritten = put + (revolutions * FIFO_entries)
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* unreadMessages = (messagesWritten - messagesRead) mod cycleSize
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* @endcode
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* In case <tt>unreadMessages > FIFO_entries</tt>, a FIFO overrun has
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* occurred. Note that in this formulation, care must be taken to avoid
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* integer overflows during computation.
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*
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* It is up to the implementation what to do on FIFO overflow. Possibly,
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* report an error and reset <tt>local_revolutions = revolutions</tt> and
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* <tt>local_get = @c put</tt>.
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* 3. If <tt>local_get == put</tt>, the are no unread messages. Exit this
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* sequence.
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* 4. Read memory barrier
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* 5. Read the message from nvs_domain_msg_fifo::messages[local_get]
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* (non-atomic read ok)
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* 6. Read memory barrier
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* 7. Atomic read nvs_domain_msg_fifo_control::put_revolutions as @c put and
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* @c revolutions
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* 8. Perform the FIFO overrun check again as in step 2. In case overrun is
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* detected, then the message read on step 5 may have been overwritten
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* while reading.
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*
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* It is up to the implementation what to do on FIFO overflow. Possibly,
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* report an error and reset <tt>local_revolutions = revolutions</tt> and
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* <tt>local_get = @c put</tt>.
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* 9. Increment <tt>local_get (mod FIFO_entries)</tt>. If there is a wrap-around,
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* increment @c local_revolutions.
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*
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* @since 1.0.0
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*/
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struct nvs_domain_msg_fifo_control {
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/**
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* @brief Get index (updated by the RW consumer)
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*
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* @remark Special value
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* #NVS_DOMAIN_MSG_FIFO_CONTROL_GET_FLOW_CTRL_DISABLED means no flow
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* control (scheduler --> client buffers only)
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*
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* @since 1.0.0
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*/
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uint32_t get;
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/**
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* @brief Padding to fill up 64B
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*/
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uint32_t reserved0[15];
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/**
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* @brief Message put index and revolution count (updated by the producer)
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*
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* This member consists of two fields:
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*
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* - The lower 32 bits is the put index
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* - The upper 32 bits is the revolution count, i.e., how many times the
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* put index has wrapped around
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*
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* For example, this field would be incremented as follows for a FIFO of size 5:
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*
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* - 0x0000'0000'0000'0000 (initial value)
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* - 0x0000'0000'0000'0001
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* - 0x0000'0000'0000'0002
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* - 0x0000'0000'0000'0003
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* - 0x0000'0000'0000'0004
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* - 0x0000'0001'0000'0000 (wrap-around, revolution count incremented)
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* - 0x0000'0001'0000'0001
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*
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* The intention of the revolution count is to provide read-only
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* observers a mechanism to detect dropped messages.
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*
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* @sa NVS_DOMAIN_MSG_FIFO_CONTROL_PUT_REVOLUTIONS_PUT_LSB
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* @sa NVS_DOMAIN_MSG_FIFO_CONTROL_PUT_REVOLUTIONS_PUT_MSB
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* @sa NVS_DOMAIN_MSG_FIFO_CONTROL_PUT_REVOLUTIONS_REVOLUTIONS_LSB
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* @sa NVS_DOMAIN_MSG_FIFO_CONTROL_PUT_REVOLUTIONS_REVOLUTIONS_MSB
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*
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* @since 1.0.0
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*/
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uint64_t put_revolutions;
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/**
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* @brief Number of dropped messages due to overrun (updated by the
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* producer)
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*
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* @since 1.0.0
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*/
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uint64_t num_dropped_messages; // number of lost messages due to buffer overrun
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/**
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* @brief Padding to fill up 64B
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*/
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uint32_t reserved1[12];
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};
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#if (defined(__cplusplus) && (__cplusplus >= 201103L))
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/* Double-check that the example in the documentation is correct */
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static_assert(
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sizeof(nvs_domain_msg_fifo_control) == 128U,
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"Verify the documented substitution (1)");
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static_assert(
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sizeof(nvs_domain_message) == 64U,
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"Verify the documented substitution (2)");
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static_assert(
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(65536U - sizeof(nvs_domain_msg_fifo_control)) / sizeof(nvs_domain_message) == 1022U,
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"Verify the documented example");
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#endif
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/**
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* @brief The general FIFO ring buffer format
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*
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* The following FIFO ring buffers are specified:
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*
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* - client --> scheduler control request messages
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* - scheduler --> client control response messages
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*
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* The FIFO must be aligned by 64 bytes.
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*
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* @since 1.0.0
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*/
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struct nvs_domain_msg_fifo {
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/**
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* @brief Message ring buffer control
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*
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* @since 1.0.0
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*/
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struct nvs_domain_msg_fifo_control control;
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/**
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* @brief Message ring buffer data
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*
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* @since 1.0.0
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*/
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struct nvs_domain_message messages[];
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};
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#if defined(__cplusplus)
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} // extern "C"
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#endif
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#endif
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