Files
linux-nvgpu/drivers/gpu/nvgpu/os/posix/timers.c
Vedashree Vidwans d6fc9d176e gpu: nvgpu: fix MISRA 17.1 in timeout_expired_msg
MISRA rule 17.1 forbids use of stdarg.h features defined for variable
arguments. This patch creates timers.h header for posix and QNX to
change nvgpu_timeout_expired_msg() to macro definition.

Jira NVGPU-4075

Change-Id: I8167f0ff7fdfb74adbbbed9c3021a9df2ad6401b
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2200885
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2020-12-15 14:05:52 -06:00

178 lines
4.1 KiB
C

/*
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <sys/time.h>
#include <time.h>
#include <nvgpu/bug.h>
#include <nvgpu/log.h>
#include <nvgpu/timers.h>
#include <nvgpu/soc.h>
#define MSEC_PER_SEC 1000
#define USEC_PER_MSEC 1000
#define NSEC_PER_USEC 1000
#define NSEC_PER_MSEC 1000000
#define NSEC_PER_SEC 1000000000
s64 nvgpu_current_time_us(void)
{
struct timeval now;
s64 time_now;
int ret;
ret = gettimeofday(&now, NULL);
if (ret != 0) {
BUG();
}
time_now = nvgpu_safe_mult_s64((s64)now.tv_sec, (s64)1000000);
time_now = nvgpu_safe_add_s64(time_now, (s64)now.tv_usec);
return time_now;
}
static s64 get_time_ns(void)
{
struct timespec ts;
s64 t_ns;
(void) clock_gettime(CLOCK_MONOTONIC, &ts);
t_ns = nvgpu_safe_mult_s64(ts.tv_sec, 1000000000);
t_ns = nvgpu_safe_add_s64(t_ns, ts.tv_nsec);
return t_ns;
}
/*
* Returns true if a > b;
*/
static bool time_after(s64 a, s64 b)
{
return (nvgpu_safe_sub_s64(a, b) > 0);
}
int nvgpu_timeout_init(struct gk20a *g, struct nvgpu_timeout *timeout,
u32 duration, unsigned long flags)
{
s64 duration_ns;
if ((flags & ~NVGPU_TIMER_FLAG_MASK) != 0U) {
return -EINVAL;
}
(void) memset(timeout, 0, sizeof(*timeout));
timeout->g = g;
timeout->flags = (unsigned int)flags;
if ((flags & NVGPU_TIMER_RETRY_TIMER) != 0U) {
timeout->retries.max_attempts = duration;
} else {
duration_ns = (s64)duration;
duration_ns = nvgpu_safe_mult_s64(duration_ns, NSEC_PER_MSEC);
timeout->time = nvgpu_safe_add_s64(nvgpu_current_time_ns(),
duration_ns);
}
return 0;
}
bool nvgpu_timeout_peek_expired(struct nvgpu_timeout *timeout)
{
if ((timeout->flags & NVGPU_TIMER_RETRY_TIMER) != 0U) {
return (timeout->retries.attempted >=
timeout->retries.max_attempts);
} else {
return time_after(get_time_ns(), timeout->time);
}
}
static void nvgpu_usleep(unsigned int usecs)
{
struct timespec rqtp;
s64 t_currentns, t_ns;
t_currentns = get_time_ns();
t_ns = (s64)usecs;
t_ns = nvgpu_safe_mult_s64(t_ns, 1000);
t_ns = nvgpu_safe_add_s64(t_ns, t_currentns);
rqtp.tv_sec = t_ns / 1000000000;
rqtp.tv_nsec = t_ns % 1000000000;
(void) clock_nanosleep(CLOCK_MONOTONIC, TIMER_ABSTIME, &rqtp, NULL);
}
void nvgpu_udelay(unsigned int usecs)
{
if (usecs >= (unsigned int) 1000) {
nvgpu_usleep(usecs);
} else {
nvgpu_delay_usecs(usecs);
}
}
void nvgpu_usleep_range(unsigned int min_us, unsigned int max_us)
{
nvgpu_udelay(min_us);
}
void nvgpu_msleep(unsigned int msecs)
{
struct timespec rqtp;
s64 t_currentns, t_ns;
t_currentns = get_time_ns();
t_ns = (s64)msecs;
t_ns = nvgpu_safe_mult_s64(t_ns, 1000000);
t_ns = nvgpu_safe_add_s64(t_ns, t_currentns);
rqtp.tv_sec = t_ns / 1000000000;
rqtp.tv_nsec = t_ns % 1000000000;
(void) clock_nanosleep(CLOCK_MONOTONIC, TIMER_ABSTIME, &rqtp, NULL);
}
s64 nvgpu_current_time_ms(void)
{
return (s64)(get_time_ns() / NSEC_PER_MSEC);
}
s64 nvgpu_current_time_ns(void)
{
return get_time_ns();
}
u64 nvgpu_hr_timestamp(void)
{
return nvgpu_get_cycles();
}
#ifdef CONFIG_NVGPU_NON_FUSA
u64 nvgpu_hr_timestamp_us(void)
{
return nvgpu_us_counter();
}
#endif