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d77785800b
MISRA Rule 10.4 only allows the usage of arithmetic operations on operands of the same essential type category. Adding "U" at the end of the integer literals to have same type of operands when an arithmetic operation is performed. This fixes violation where an arithmetic operation is performed on signed and unsigned int types. JIRA NVGPU-992 Change-Id: Ic9a911beb6d161df950ca85eb4813547603a8743 Signed-off-by: Sai Nikhil <snikhil@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1809751 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
144 lines
4.2 KiB
C
144 lines
4.2 KiB
C
/*
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* general p state infrastructure
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*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_CTRLVOLT_H
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#define NVGPU_CTRLVOLT_H
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#define CTRL_VOLT_VOLT_RAIL_MAX_RAILS \
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CTRL_BOARDOBJGRP_E32_MAX_OBJECTS
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#include "ctrlperf.h"
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#include "ctrlboardobj.h"
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#define CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES 0x04U
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#define CTRL_VOLT_VOLT_DEV_VID_VSEL_MAX_ENTRIES (8U)
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#define CTRL_VOLT_DOMAIN_INVALID 0x00U
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#define CTRL_VOLT_DOMAIN_LOGIC 0x01U
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#define CLK_PROG_VFE_ENTRY_LOGIC 0x00U
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#define CLK_PROG_VFE_ENTRY_SRAM 0x01U
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/*
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* Macros for Voltage Domain HAL.
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*/
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#define CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL 0x00U
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#define CTRL_VOLT_DOMAIN_HAL_GP10X_SPLIT_RAIL 0x01U
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/*
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* Macros for Voltage Domains.
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*/
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#define CTRL_VOLT_DOMAIN_INVALID 0x00U
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#define CTRL_VOLT_DOMAIN_LOGIC 0x01U
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#define CTRL_VOLT_DOMAIN_SRAM 0x02U
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/*!
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* Special value corresponding to an invalid Voltage Rail Index.
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*/
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#define CTRL_VOLT_RAIL_INDEX_INVALID \
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CTRL_BOARDOBJ_IDX_INVALID
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/*!
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* Special value corresponding to an invalid Voltage Device Index.
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*/
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#define CTRL_VOLT_DEVICE_INDEX_INVALID \
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CTRL_BOARDOBJ_IDX_INVALID
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/*!
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* Special value corresponding to an invalid Voltage Policy Index.
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*/
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#define CTRL_VOLT_POLICY_INDEX_INVALID \
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CTRL_BOARDOBJ_IDX_INVALID
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enum nv_pmu_pmgr_pwm_source {
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NV_PMU_PMGR_PWM_SOURCE_INVALID = 0,
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NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_0 = 4,
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NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_1,
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NV_PMU_PMGR_PWM_SOURCE_RSVD_0 = 7,
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NV_PMU_PMGR_PWM_SOURCE_RSVD_1 = 8,
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};
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/*!
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* Macros for Voltage Device Types.
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*/
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#define CTRL_VOLT_DEVICE_TYPE_INVALID 0x00U
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#define CTRL_VOLT_DEVICE_TYPE_PWM 0x03U
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/*
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* Macros for Volt Device Operation types.
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*/
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#define CTRL_VOLT_DEVICE_OPERATION_TYPE_INVALID 0x00U
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#define CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT 0x01U
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#define CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_STEADY_STATE 0x02U
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#define CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_SLEEP_STATE 0x03U
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#define CTRL_VOLT_VOLT_DEVICE_OPERATION_TYPE_IPC_VMIN 0x04U
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/*!
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* Macros for Voltage Domains.
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*/
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#define CTRL_VOLT_DOMAIN_INVALID 0x00U
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#define CTRL_VOLT_DOMAIN_LOGIC 0x01U
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#define CTRL_VOLT_DOMAIN_SRAM 0x02U
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/*!
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* Macros for Volt Policy types.
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*
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* Virtual VOLT_POLICY types are indexed starting from 0xFF.
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*/
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#define CTRL_VOLT_POLICY_TYPE_INVALID 0x00U
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#define CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL 0x01U
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#define CTRL_VOLT_POLICY_TYPE_SR_MULTI_STEP 0x02U
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#define CTRL_VOLT_POLICY_TYPE_SR_SINGLE_STEP 0x03U
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#define CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL_MULTI_STEP 0x04U
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#define CTRL_VOLT_POLICY_TYPE_SPLIT_RAIL 0xFEU
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#define CTRL_VOLT_POLICY_TYPE_UNKNOWN 0xFFU
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/*!
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* Macros for Volt Policy Client types.
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*/
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#define CTRL_VOLT_POLICY_CLIENT_INVALID 0x00U
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#define CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ 0x01U
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struct ctrl_volt_volt_rail_list_item {
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u8 rail_idx;
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u32 voltage_uv;
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};
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struct ctrl_volt_volt_rail_list {
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u8 num_rails;
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struct ctrl_volt_volt_rail_list_item
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rails[CTRL_VOLT_VOLT_RAIL_MAX_RAILS];
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};
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struct ctrl_volt_volt_rail_list_item_v1 {
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u8 rail_idx;
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u32 voltage_uv;
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u32 voltage_min_noise_unaware_uv;
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};
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struct ctrl_volt_volt_rail_list_v1 {
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u8 num_rails;
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struct ctrl_volt_volt_rail_list_item_v1
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rails[CTRL_VOLT_VOLT_RAIL_MAX_RAILS];
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};
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#endif /* NVGPU_CTRLVOLT_H */
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