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git://nv-tegra.nvidia.com/linux-nvgpu.git
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9dd2a8fc73
The memory bandwidth reported by the nvgpu driver is a resultant of FBP and EMC floorsweeping status. The FBP floorsweep status was already getting reported in the GPU characterstics so the status of EMC was fetched and reported in this change. Jira NVGPU-9609 Bug 3661074 Change-Id: Ia2fe6cb029d086765da15d9e964ea77256e06604 Signed-off-by: atanand <atanand@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2859237 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
106 lines
2.6 KiB
C
106 lines
2.6 KiB
C
/*
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* Copyright (c) 2017-2023, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <nvgpu/fuse.h>
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#include <nvgpu/linux/soc_fuse.h>
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#include <nvgpu/linux/nvmem.h>
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#include <soc/tegra/fuse.h>
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int nvgpu_tegra_get_gpu_speedo_id(struct gk20a *g, int *id)
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{
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*id = tegra_sku_info.gpu_speedo_id;
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return 0;
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}
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int nvgpu_tegra_fuse_read_reserved_calib(struct gk20a *g, u32 *val)
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{
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#ifdef CONFIG_NVGPU_NVMEM_FUSE
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return nvgpu_tegra_nvmem_read_reserved_calib(g, val);
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#else
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return tegra_fuse_readl(FUSE_RESERVED_CALIB0_0, val);
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#endif
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}
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int nvgpu_tegra_fuse_read_gcplex_config_fuse(struct gk20a *g, u32 *val)
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{
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#ifdef CONFIG_NVGPU_NVMEM_FUSE
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return nvgpu_tegra_nvmem_read_gcplex_config_fuse(g, val);
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#else
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return tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, val);
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#endif
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}
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int nvgpu_tegra_fuse_read_opt_gpc_disable(struct gk20a *g, u32 *val)
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{
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return tegra_fuse_readl(FUSE_OPT_GPC_DISABLE_0, val);
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}
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int nvgpu_tegra_fuse_read_opt_emc_disable(struct gk20a *g, u32 *val)
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{
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return tegra_fuse_readl(FUSE_OPT_EMC_DISABLE_0, val);
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}
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int nvgpu_tegra_fuse_read_per_device_identifier(struct gk20a *g, u64 *pdi)
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{
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#ifdef CONFIG_NVGPU_NVMEM_FUSE
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return nvgpu_tegra_nvmem_read_per_device_identifier(g, pdi);
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#else
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u32 lo = 0U;
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u32 hi = 0U;
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int err;
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err = tegra_fuse_readl(FUSE_PDI0, &lo);
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if (err)
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return err;
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err = tegra_fuse_readl(FUSE_PDI1, &hi);
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if (err)
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return err;
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*pdi = ((u64)lo) | (((u64)hi) << 32);
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return 0;
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#endif
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}
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#ifdef CONFIG_NVGPU_TEGRA_FUSE
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/*
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* Use tegra_fuse_control_read/write() APIs for fuse offsets upto 0x100
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* Use tegra_fuse_readl/writel() APIs for fuse offsets above 0x100
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*/
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void nvgpu_tegra_fuse_write_bypass(struct gk20a *g, u32 val)
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{
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tegra_fuse_control_write(val, FUSE_FUSEBYPASS_0);
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}
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void nvgpu_tegra_fuse_write_access_sw(struct gk20a *g, u32 val)
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{
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tegra_fuse_control_write(val, FUSE_WRITE_ACCESS_SW_0);
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}
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void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(struct gk20a *g, u32 val)
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{
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tegra_fuse_writel(val, FUSE_OPT_GPU_TPC0_DISABLE_0);
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}
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void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(struct gk20a *g, u32 val)
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{
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tegra_fuse_writel(val, FUSE_OPT_GPU_TPC1_DISABLE_0);
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}
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#endif /* CONFIG_NVGPU_TEGRA_FUSE */
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