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876feb8842
Jira NVGPU-5435 Change-Id: I5ab7a2f45d094a316c97ffd980e128e21947b97f Signed-off-by: shashank singh <shashsingh@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2360777 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
59 lines
2.0 KiB
C
59 lines
2.0 KiB
C
/*
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* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef CLK_MON_TU104_H
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#define CLK_MON_TU104_H
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/**
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* FMON register types
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*/
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#define FMON_THRESHOLD_HIGH 0x0U
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#define FMON_THRESHOLD_LOW 0x1U
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#define FMON_FAULT_STATUS 0x2U
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#define FMON_FAULT_STATUS_PRIV_MASK 0x3U
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#define CLK_CLOCK_MON_REG_TYPE_COUNT 0x4U
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#define CLK_MON_BITS_PER_BYTE 0x8U
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/*
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* The Maximum count of clock domains supported
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*/
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#define CLK_CLOCK_MON_DOMAIN_COUNT 0x32U
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struct clk_domain_mon_status {
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u32 clk_api_domain;
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u32 low_threshold;
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u32 high_threshold;
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u32 clk_domain_fault_status;
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};
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struct clk_domains_mon_status_params {
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u32 clk_mon_domain_mask;
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struct clk_domain_mon_status
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clk_mon_list[CLK_CLOCK_MON_DOMAIN_COUNT];
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};
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bool tu104_clk_mon_check_master_fault_status(struct gk20a *g);
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int tu104_clk_mon_check_status(struct gk20a *g, u32 domain_mask);
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bool tu104_clk_mon_check_clk_good(struct gk20a *g);
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bool tu104_clk_mon_check_pll_lock(struct gk20a *g);
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#endif /* CLK_MON_TU104_H */
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