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gpu: nvgpu: fix incorrect clk hal names

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Jira NVGPU-5435

Change-Id: I5ab7a2f45d094a316c97ffd980e128e21947b97f
Signed-off-by: shashank singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2360777
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
shashank singh
2020-06-12 11:22:22 +05:30
committed by Alex Waterman
parent e7d6d36a16
commit 876feb8842
3 changed files with 13 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/gpu/nvgpu/hal/clk/clk_mon_tu104.c
View File

@@ -178,7 +178,7 @@ static int nvgpu_clk_mon_get_fault(struct gk20a *g, u32 i, u32 data,
return status;
}
bool nvgpu_clk_mon_check_master_fault_status(struct gk20a *g)
bool tu104_clk_mon_check_master_fault_status(struct gk20a *g)
{
u32 fmon_master_status = nvgpu_readl(g, trim_fmon_master_status_r());
@@ -207,7 +207,7 @@ int nvgpu_clk_mon_alloc_memory(struct gk20a *g)
return 0;
}
int nvgpu_clk_mon_check_status(struct gk20a *g, u32 domain_mask)
int tu104_clk_mon_check_status(struct gk20a *g, u32 domain_mask)
{
u32 reg_address, bit_pos;
u32 data;
@@ -247,7 +247,7 @@ int nvgpu_clk_mon_check_status(struct gk20a *g, u32 domain_mask)
return 0;
}
bool nvgpu_clk_mon_check_clk_good(struct gk20a *g)
bool tu104_clk_mon_check_clk_good(struct gk20a *g)
{
u32 clk_status = nvgpu_readl(g, trim_xtal4x_cfg5_r());
@@ -258,7 +258,7 @@ bool nvgpu_clk_mon_check_clk_good(struct gk20a *g)
return false;
}
bool nvgpu_clk_mon_check_pll_lock(struct gk20a *g)
bool tu104_clk_mon_check_pll_lock(struct gk20a *g)
{
u32 clk_status = nvgpu_readl(g, trim_xtal4x_cfg_r());

9
drivers/gpu/nvgpu/hal/clk/clk_mon_tu104.h
View File

@@ -50,8 +50,9 @@ struct clk_domains_mon_status_params {
clk_mon_list[CLK_CLOCK_MON_DOMAIN_COUNT];
};
bool nvgpu_clk_mon_check_master_fault_status(struct gk20a *g);
int nvgpu_clk_mon_check_status(struct gk20a *g, u32 domain_mask);
bool nvgpu_clk_mon_check_clk_good(struct gk20a *g);
bool nvgpu_clk_mon_check_pll_lock(struct gk20a *g);
bool tu104_clk_mon_check_master_fault_status(struct gk20a *g);
int tu104_clk_mon_check_status(struct gk20a *g, u32 domain_mask);
bool tu104_clk_mon_check_clk_good(struct gk20a *g);
bool tu104_clk_mon_check_pll_lock(struct gk20a *g);
#endif /* CLK_MON_TU104_H */

8
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -1318,10 +1318,10 @@ static const struct gpu_ops tu104_ops = {
.clk_mon = {
.clk_mon_alloc_memory = nvgpu_clk_mon_alloc_memory,
.clk_mon_check_master_fault_status =
nvgpu_clk_mon_check_master_fault_status,
.clk_mon_check_status = nvgpu_clk_mon_check_status,
.clk_mon_check_clk_good = nvgpu_clk_mon_check_clk_good,
.clk_mon_check_pll_lock = nvgpu_clk_mon_check_pll_lock,
tu104_clk_mon_check_master_fault_status,
.clk_mon_check_status = tu104_clk_mon_check_status,
.clk_mon_check_clk_good = tu104_clk_mon_check_clk_good,
.clk_mon_check_pll_lock = tu104_clk_mon_check_pll_lock,
},
#ifdef CONFIG_NVGPU_CLK_ARB