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fba96fdc09
Delete the struct nvgpu_engine_info as it's essentially identical to
struct nvgpu_device. Duplicating data structures is not ideal as it's
terribly confusing what does what.
Update all uses of nvgpu_engine_info to use struct nvgpu_device. This
is often a fairly straight forward replacement. Couple of places though
where things got interesting:
- The enum_type that engine_info uses is defined in engines.h and
has a bit of SW abstraction - in particular the GRCE type. The only
place this seemed to be actually relevant (the IOCTL providing device
info to userspace) the GRCE engines can be worked out by comparing
runlist ID.
- Addition of masks based on intr_id and reset_id; those can be
computed easily enough using BIT32() but this is an area that
could be improved on.
This reaches into a lot of extraneous code that traverses the fifo
active engines list and dramtically simplifies this. Now, instead of
having to go through a table of engine IDs that point to the list of
all host engines, the active engine list is just a list of pointers to
valid engines. It's now trivial to do a for-all-active-engines type
loop. This could even be turned into a generic macro or otherwise
abstracted in the future.
JIRA NVGPU-5421
Change-Id: I3a810deb55a7dd8c09836fd2dae85d3e28eb23cf
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2319895
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
71 lines
2.4 KiB
C
71 lines
2.4 KiB
C
/*
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* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/kmem.h>
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#include <nvgpu/device.h>
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#include <nvgpu/engines.h>
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#include <nvgpu/vgpu/vgpu.h>
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#include "top_vgpu.h"
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/*
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* Similar to how the real HW version works, just read a device out of the vGPU
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* device list one at a time. The core device management code will manage the
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* actual device lists for us.
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*/
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struct nvgpu_device *vgpu_top_parse_next_dev(struct gk20a *g, u32 *token)
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{
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struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
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struct tegra_vgpu_engines_info *engines = &priv->constants.engines_info;
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struct nvgpu_device *dev;
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/*
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* Check to see if we are done parsing engines.
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*/
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if (*token >= engines->num_engines) {
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return NULL;
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}
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dev = nvgpu_kzalloc(g, sizeof(*dev));
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if (!dev) {
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return NULL;
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}
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/*
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* Copy the engine data into the device and return it to our caller.
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*/
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dev->type = engines->info[*token].engine_enum;
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dev->engine_id = engines->info[*token].engine_id;
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dev->intr_id = nvgpu_ffs(engines->info[*token].intr_mask) - 1;
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dev->reset_id = nvgpu_ffs(engines->info[*token].reset_mask) - 1;
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dev->runlist_id = engines->info[*token].runlist_id;
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dev->pbdma_id = engines->info[*token].pbdma_id;
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dev->inst_id = engines->info[*token].inst_id;
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dev->pri_base = engines->info[*token].pri_base;
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dev->fault_id = engines->info[*token].fault_id;
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(*token)++;
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return dev;
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}
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