Engine falcon reset, emem copy and queue head/tail management has to be accessed through hal APIs. Introduce these for PMU & SEC2 engines. JIRA NVGPU-1459 Change-Id: I1d8f5103decb0bcba387886304d899ecc7b42cf1 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2016282 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>