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This CL covers the following modifications, 1) Added logic to skip the graphics unit specific sw context load register write during context creation when MIG is enabled. 2) Added logic to skip the graphics unit specific sw method register write when MIG is enabled. 3) Added logic to skip the graphics unit specific slcg and blcg gr register write when MIG is enabled. 4) Fixed some priv errors observed during MIG boot. 5) Added MIG Physical support for GPU count < 1. 6) Host clk register access is not allowed for GA100. So skipped to access host clk register. 7) Added utiliy api - nvgpu_gr_exec_with_ret_for_all_instances() 8) Added gr_pri_mme_shadow_ram_index_nvclass_v() reg field to identify the sw method class number. Bug 200649233 Change-Id: Ie434226f007ee5df75a506fedeeb10c3d6e227a3 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2549811 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
21 KiB
21 KiB