Divya Singhatwaria 4d02580df0 gpu: nvgpu: remove ZBC save/restore by PMU ...

- ZBC save/restore registers are removed in GP10B PMU ucode.
- These registers are saved/restored from CTXSW ucode during
  ELPG entry/exit.
- Accessing the ZBC registers will cause PMU EXTERR error.
- To resolve this, ZBC functionality is removed from GP10B
  feature list in PMU ucode.
- From NvGPU driver, set NVGPU_PMU_ZBC_SAVE bit to false
  for GP10B
- Updated the GP10B PMU app version for the ucode:
  https://git-master.nvidia.com/r/c/tegra/kernel-firmware-t18x/+/2476260

P4 CL link related to this PMU ucode change:
https://p4sw-swarm.nvidia.com/changes/29594520

Bug 3233071
Bug 200696431

Change-Id: If3f1707b79699e7e2e65367418b25ac71b09cf0b
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
(cherry picked from commit 9170f2b77c)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2500641
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2021-03-24 03:36:40 -07:00

..

fw_ns_bootstrap.c

gpu: nvgpu: Add RISCV LS PMU support

2020-12-17 18:36:44 -06:00

fw_ver_ops.c

gpu: nvgpu: remove ZBC save/restore by PMU

2021-03-24 03:36:40 -07:00

fw.c

gpu: nvgpu: PMU NS bootstrap on next core

2020-12-15 14:13:28 -06:00