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9bb347edec
Various gv11b register accessors are passed as function pointer to NVGPU_ECC_ERR. pmu logic needs access to head, tail, mutex registers as function pointers. fix the same. JIRA NVGPU-3733 Change-Id: I5668fedaac187fab052ee5d68a10f7e2d6d35413 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2150880 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
191 lines
5.4 KiB
C
191 lines
5.4 KiB
C
/*
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* Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/pmu.h>
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#include <nvgpu/log.h>
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#include <nvgpu/io.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/bug.h>
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#include <nvgpu/pmu/cmd.h>
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#include "pmu_gk20a.h"
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#include "pmu_gp10b.h"
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#include <nvgpu/hw/gp10b/hw_pwr_gp10b.h>
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/* PROD settings for ELPG sequencing registers*/
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static struct pg_init_sequence_list _pginitseq_gp10b[] = {
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{0x0010ab10U, 0x0000868BU} ,
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{0x0010e118U, 0x8590848FU} ,
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{0x0010e000U, 0x0U} ,
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{0x0010e06cU, 0x000000A3U} ,
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{0x0010e06cU, 0x000000A0U} ,
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{0x0010e06cU, 0x00000095U} ,
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{0x0010e06cU, 0x000000A6U} ,
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{0x0010e06cU, 0x0000008CU} ,
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{0x0010e06cU, 0x00000080U} ,
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{0x0010e06cU, 0x00000081U} ,
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{0x0010e06cU, 0x00000087U} ,
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{0x0010e06cU, 0x00000088U} ,
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{0x0010e06cU, 0x0000008DU} ,
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{0x0010e06cU, 0x00000082U} ,
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{0x0010e06cU, 0x00000083U} ,
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{0x0010e06cU, 0x00000089U} ,
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{0x0010e06cU, 0x0000008AU} ,
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{0x0010e06cU, 0x000000A2U} ,
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{0x0010e06cU, 0x00000097U} ,
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{0x0010e06cU, 0x00000092U} ,
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{0x0010e06cU, 0x00000099U} ,
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{0x0010e06cU, 0x0000009BU} ,
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{0x0010e06cU, 0x0000009DU} ,
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{0x0010e06cU, 0x0000009FU} ,
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{0x0010e06cU, 0x000000A1U} ,
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{0x0010e06cU, 0x00000096U} ,
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{0x0010e06cU, 0x00000091U} ,
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{0x0010e06cU, 0x00000098U} ,
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{0x0010e06cU, 0x0000009AU} ,
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{0x0010e06cU, 0x0000009CU} ,
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{0x0010e06cU, 0x0000009EU} ,
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{0x0010ab14U, 0x00000000U} ,
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{0x0010e024U, 0x00000000U} ,
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{0x0010e028U, 0x00000000U} ,
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{0x0010e11cU, 0x00000000U} ,
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{0x0010ab1cU, 0x140B0BFFU} ,
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{0x0010e020U, 0x0E2626FFU} ,
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{0x0010e124U, 0x251010FFU} ,
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{0x0010ab20U, 0x89abcdefU} ,
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{0x0010ab24U, 0x00000000U} ,
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{0x0010e02cU, 0x89abcdefU} ,
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{0x0010e030U, 0x00000000U} ,
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{0x0010e128U, 0x89abcdefU} ,
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{0x0010e12cU, 0x00000000U} ,
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{0x0010ab28U, 0x7FFFFFFFU} ,
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{0x0010ab2cU, 0x70000000U} ,
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{0x0010e034U, 0x7FFFFFFFU} ,
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{0x0010e038U, 0x70000000U} ,
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{0x0010e130U, 0x7FFFFFFFU} ,
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{0x0010e134U, 0x70000000U} ,
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{0x0010ab30U, 0x00000000U} ,
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{0x0010ab34U, 0x00000001U} ,
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{0x00020004U, 0x00000000U} ,
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{0x0010e138U, 0x00000000U} ,
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{0x0010e040U, 0x00000000U} ,
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{0x0010e168U, 0x00000000U} ,
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{0x0010e114U, 0x0000A5A4U} ,
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{0x0010e110U, 0x00000000U} ,
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{0x0010e10cU, 0x8590848FU} ,
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{0x0010e05cU, 0x00000000U} ,
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{0x0010e044U, 0x00000000U} ,
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{0x0010a644U, 0x0000868BU} ,
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{0x0010a648U, 0x00000000U} ,
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{0x0010a64cU, 0x00829493U} ,
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{0x0010a650U, 0x00000000U} ,
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{0x0010e000U, 0x0U} ,
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{0x0010e068U, 0x000000A3U} ,
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{0x0010e068U, 0x000000A0U} ,
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{0x0010e068U, 0x00000095U} ,
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{0x0010e068U, 0x000000A6U} ,
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{0x0010e068U, 0x0000008CU} ,
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{0x0010e068U, 0x00000080U} ,
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{0x0010e068U, 0x00000081U} ,
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{0x0010e068U, 0x00000087U} ,
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{0x0010e068U, 0x00000088U} ,
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{0x0010e068U, 0x0000008DU} ,
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{0x0010e068U, 0x00000082U} ,
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{0x0010e068U, 0x00000083U} ,
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{0x0010e068U, 0x00000089U} ,
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{0x0010e068U, 0x0000008AU} ,
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{0x0010e068U, 0x000000A2U} ,
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{0x0010e068U, 0x00000097U} ,
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{0x0010e068U, 0x00000092U} ,
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{0x0010e068U, 0x00000099U} ,
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{0x0010e068U, 0x0000009BU} ,
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{0x0010e068U, 0x0000009DU} ,
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{0x0010e068U, 0x0000009FU} ,
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{0x0010e068U, 0x000000A1U} ,
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{0x0010e068U, 0x00000096U} ,
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{0x0010e068U, 0x00000091U} ,
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{0x0010e068U, 0x00000098U} ,
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{0x0010e068U, 0x0000009AU} ,
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{0x0010e068U, 0x0000009CU} ,
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{0x0010e068U, 0x0000009EU} ,
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{0x0010e000U, 0x0U} ,
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{0x0010e004U, 0x0000008EU},
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};
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void gp10b_pmu_setup_elpg(struct gk20a *g)
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{
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size_t reg_writes;
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size_t index;
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nvgpu_log_fn(g, " ");
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if (g->can_elpg && g->elpg_enabled) {
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reg_writes = ARRAY_SIZE(_pginitseq_gp10b);
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/* Initialize registers with production values*/
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for (index = 0; index < reg_writes; index++) {
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gk20a_writel(g, _pginitseq_gp10b[index].regaddr,
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_pginitseq_gp10b[index].writeval);
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}
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}
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nvgpu_log_fn(g, "done");
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}
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void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr)
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{
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gk20a_writel(g, pwr_falcon_dmatrfbase_r(),
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addr);
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gk20a_writel(g, pwr_falcon_dmatrfbase1_r(),
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0x0U);
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}
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bool gp10b_is_pmu_supported(struct gk20a *g)
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{
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return true;
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}
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u32 gp10b_pmu_queue_head_r(u32 i)
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{
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return pwr_pmu_queue_head_r(i);
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}
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u32 gp10b_pmu_queue_head__size_1_v(void)
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{
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return pwr_pmu_queue_head__size_1_v();
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}
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u32 gp10b_pmu_queue_tail_r(u32 i)
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{
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return pwr_pmu_queue_tail_r(i);
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}
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u32 gp10b_pmu_queue_tail__size_1_v(void)
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{
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return pwr_pmu_queue_tail__size_1_v();
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}
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u32 gp10b_pmu_mutex__size_1_v(void)
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{
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return pwr_pmu_mutex__size_1_v();
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}
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