linux-nvgpu

mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-23 18:16:01 +03:00

Files

Deepak Nibade b23a114c63 gpu: nvgpu: ensure all perfmon writes are complete after reset

gr_gv100_reset_hwpm_pmm_registers() writes a bunch of registers in
sys/gpc/fbp chiplets to reset perfmons. To ensure all the writes have
completed it is necessary to readback each chiplet's PRI fence register.

Add and use new HAL g->ops.priv_ring.read_pri_fence() to achieve this.

Implement the HAL for gv11b in new source code file
hal/priv_ring/priv_ring_gv11b.c.

Bug 2510974
Jira NVGPU-5360

Change-Id: If4dd61cb4265422e8c2d16884790eb0fe7f2c103
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2453631
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>

2020-12-15 14:13:48 -06:00

priv_ring_gm20b_fusa.c

gpu: nvgpu: gm20b: enable priv_ring interrupts for sim

2020-12-15 14:13:28 -06:00

priv_ring_gm20b.c

gpu: nvgpu: move safe code HAL files to fusa

2019-07-03 02:46:15 -07:00

priv_ring_gm20b.h

gpu: nvgpu: init: add return for all init APIs

2020-12-15 14:05:52 -06:00

priv_ring_gp10b_fusa.c

gpu: nvgpu: add isr_handle_0/1 priv_ring gops