mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-22 09:12:24 +03:00
131 lines
3.4 KiB
C
131 lines
3.4 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/kmem.h>
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#include <nvgpu/log.h>
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#include <nvgpu/fbp.h>
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#include <nvgpu/static_analysis.h>
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#include "fbp_priv.h"
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int nvgpu_fbp_init_support(struct gk20a *g)
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{
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struct nvgpu_fbp *fbp;
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u32 fbp_en_mask;
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#ifdef CONFIG_NVGPU_NON_FUSA
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u32 max_ltc_per_fbp;
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u32 rop_l2_all_en;
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unsigned long i;
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unsigned long fbp_en_mask_tmp;
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u32 tmp;
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#endif
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if (g->fbp != NULL) {
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return 0;
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}
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fbp = nvgpu_kzalloc(g, sizeof(*fbp));
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if (fbp == NULL) {
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return -ENOMEM;
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}
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#ifdef CONFIG_NVGPU_NON_FUSA
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fbp->num_fbps = g->ops.priv_ring.get_fbp_count(g);
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nvgpu_log_info(g, "fbps: %d", fbp->num_fbps);
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#endif
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fbp->max_fbps_count = g->ops.top.get_max_fbps_count(g);
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nvgpu_log_info(g, "max_fbps_count: %d", fbp->max_fbps_count);
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/*
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* Read active fbp mask from fuse
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* Note that 0:enable and 1:disable in value read from fuse so we've to
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* flip the bits.
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* Also set unused bits to zero
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*/
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fbp_en_mask = g->ops.fuse.fuse_status_opt_fbp(g);
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fbp_en_mask = ~fbp_en_mask;
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fbp_en_mask = fbp_en_mask &
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nvgpu_safe_sub_u32(BIT32(fbp->max_fbps_count), 1U);
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fbp->fbp_en_mask = fbp_en_mask;
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#ifdef CONFIG_NVGPU_NON_FUSA
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fbp->fbp_rop_l2_en_mask =
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nvgpu_kzalloc(g,
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nvgpu_safe_mult_u64(fbp->max_fbps_count, sizeof(u32)));
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if (fbp->fbp_rop_l2_en_mask == NULL) {
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nvgpu_kfree(g, fbp);
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return -ENOMEM;
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}
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fbp_en_mask_tmp = fbp_en_mask;
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max_ltc_per_fbp = g->ops.top.get_max_ltc_per_fbp(g);
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rop_l2_all_en = nvgpu_safe_sub_u32(BIT32(max_ltc_per_fbp), 1U);
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/* mask of Rop_L2 for each FBP */
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for_each_set_bit(i, &fbp_en_mask_tmp, fbp->max_fbps_count) {
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tmp = g->ops.fuse.fuse_status_opt_rop_l2_fbp(g, i);
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fbp->fbp_rop_l2_en_mask[i] = rop_l2_all_en ^ tmp;
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}
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#endif
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g->fbp = fbp;
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return 0;
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}
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void nvgpu_fbp_remove_support(struct gk20a *g)
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{
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struct nvgpu_fbp *fbp = g->fbp;
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if (fbp != NULL) {
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nvgpu_kfree(g, fbp->fbp_rop_l2_en_mask);
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nvgpu_kfree(g, fbp);
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}
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g->fbp = NULL;
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}
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u32 nvgpu_fbp_get_max_fbps_count(struct nvgpu_fbp *fbp)
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{
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return fbp->max_fbps_count;
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}
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u32 nvgpu_fbp_get_fbp_en_mask(struct nvgpu_fbp *fbp)
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{
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return fbp->fbp_en_mask;
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}
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#ifdef CONFIG_NVGPU_NON_FUSA
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u32 nvgpu_fbp_get_num_fbps(struct nvgpu_fbp *fbp)
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{
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return fbp->num_fbps;
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}
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u32 *nvgpu_fbp_get_rop_l2_en_mask(struct nvgpu_fbp *fbp)
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{
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return fbp->fbp_rop_l2_en_mask;
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}
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#endif
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