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This patch removes the dependency on the header file "uapi/linux/nvgpu.h" for regops_gk20a.c. The original structure and definitions in the uapi/linux/nvgpu.h is maintained for userspace libnvrm_gpu.h. The following changes are made in this patch. 1) Defined common versions of the NVGPU_DBG_GPU_REG_OP* definitions inside regops_gk20a.h. 2) Defined common version of struct nvgpu_dbg_gpu_reg_op inside regops_gk20a.h naming it struct nvgpu_dbg_reg_op. 3) Constructed APIs to convert the NVGPU_DBG_GPU_REG_OP* definitions from linux versions to common and vice versa. 4) Constructed APIs to convert from struct nvgpu_dbg_gpu_reg_op to struct nvgpu_dbg_reg_op and vice versa. 5) The ioctl handler nvgpu_ioctl_channel_reg_ops first copies from userspace into a local storage based on struct nvgpu_dbg_gpu_reg_op which is copied into the struct nvgpu_dbg_reg_op using the APIs above and after executing the regops handler passes the data back into userspace by copying back data from struct nvgpu_dbg_reg_op to struct nvgpu_dbg_gpu_reg_opi. JIRA NVGPU-417 Change-Id: I23bad48d2967a629a6308c7484f3741a89db6537 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1596972 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
212 lines
5.6 KiB
C
212 lines
5.6 KiB
C
/*
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* Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/tegra_gr_comm.h>
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#include <linux/tegra_vgpu.h>
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#include <uapi/linux/nvgpu.h>
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#include "gk20a/gk20a.h"
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#include "gk20a/channel_gk20a.h"
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#include "gk20a/dbg_gpu_gk20a.h"
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#include "gk20a/regops_gk20a.h"
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#include "vgpu.h"
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#include "dbg_vgpu.h"
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#include <nvgpu/bug.h>
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int vgpu_exec_regops(struct dbg_session_gk20a *dbg_s,
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struct nvgpu_dbg_reg_op *ops,
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u64 num_ops)
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{
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struct channel_gk20a *ch;
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struct tegra_vgpu_cmd_msg msg;
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struct tegra_vgpu_reg_ops_params *p = &msg.params.reg_ops;
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void *oob;
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size_t oob_size, ops_size;
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void *handle = NULL;
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int err = 0;
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gk20a_dbg_fn("");
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BUG_ON(sizeof(*ops) != sizeof(struct tegra_vgpu_reg_op));
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handle = tegra_gr_comm_oob_get_ptr(TEGRA_GR_COMM_CTX_CLIENT,
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tegra_gr_comm_get_server_vmid(),
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TEGRA_VGPU_QUEUE_CMD,
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&oob, &oob_size);
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if (!handle)
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return -EINVAL;
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ops_size = sizeof(*ops) * num_ops;
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if (oob_size < ops_size) {
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err = -ENOMEM;
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goto fail;
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}
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memcpy(oob, ops, ops_size);
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msg.cmd = TEGRA_VGPU_CMD_REG_OPS;
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msg.handle = vgpu_get_handle(dbg_s->g);
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ch = nvgpu_dbg_gpu_get_session_channel(dbg_s);
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p->handle = ch ? ch->virt_ctx : 0;
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p->num_ops = num_ops;
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p->is_profiler = dbg_s->is_profiler;
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err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
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err = err ? err : msg.ret;
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if (!err)
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memcpy(ops, oob, ops_size);
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fail:
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tegra_gr_comm_oob_put_ptr(handle);
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return err;
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}
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int vgpu_dbg_set_powergate(struct dbg_session_gk20a *dbg_s, bool disable_powergate)
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{
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struct tegra_vgpu_cmd_msg msg;
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struct tegra_vgpu_set_powergate_params *p = &msg.params.set_powergate;
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int err = 0;
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u32 mode;
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gk20a_dbg_fn("");
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/* Just return if requested mode is the same as the session's mode */
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if (disable_powergate) {
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if (dbg_s->is_pg_disabled)
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return 0;
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dbg_s->is_pg_disabled = true;
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mode = NVGPU_DBG_GPU_POWERGATE_MODE_DISABLE;
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} else {
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if (!dbg_s->is_pg_disabled)
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return 0;
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dbg_s->is_pg_disabled = false;
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mode = NVGPU_DBG_GPU_POWERGATE_MODE_ENABLE;
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}
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msg.cmd = TEGRA_VGPU_CMD_SET_POWERGATE;
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msg.handle = vgpu_get_handle(dbg_s->g);
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p->mode = mode;
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err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
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err = err ? err : msg.ret;
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return err;
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}
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static int vgpu_sendrecv_prof_cmd(struct dbg_session_gk20a *dbg_s, u32 mode)
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{
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struct tegra_vgpu_cmd_msg msg;
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struct tegra_vgpu_prof_mgt_params *p = &msg.params.prof_management;
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int err = 0;
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msg.cmd = TEGRA_VGPU_CMD_PROF_MGT;
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msg.handle = vgpu_get_handle(dbg_s->g);
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p->mode = mode;
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err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
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err = err ? err : msg.ret;
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return err;
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}
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bool vgpu_check_and_set_global_reservation(
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struct dbg_session_gk20a *dbg_s,
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struct dbg_profiler_object_data *prof_obj)
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{
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struct gk20a *g = dbg_s->g;
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if (g->profiler_reservation_count > 0)
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return false;
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/* Check that another guest OS doesn't already have a reservation */
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if (!vgpu_sendrecv_prof_cmd(dbg_s, TEGRA_VGPU_PROF_GET_GLOBAL)) {
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g->global_profiler_reservation_held = true;
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g->profiler_reservation_count = 1;
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dbg_s->has_profiler_reservation = true;
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prof_obj->has_reservation = true;
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return true;
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}
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return false;
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}
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bool vgpu_check_and_set_context_reservation(
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struct dbg_session_gk20a *dbg_s,
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struct dbg_profiler_object_data *prof_obj)
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{
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struct gk20a *g = dbg_s->g;
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/* Assumes that we've already checked that no global reservation
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* is in effect for this guest.
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*
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* If our reservation count is non-zero, then no other guest has the
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* global reservation; if it is zero, need to check with RM server.
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*
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*/
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if ((g->profiler_reservation_count != 0) ||
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!vgpu_sendrecv_prof_cmd(dbg_s, TEGRA_VGPU_PROF_GET_CONTEXT)) {
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g->profiler_reservation_count++;
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dbg_s->has_profiler_reservation = true;
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prof_obj->has_reservation = true;
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return true;
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}
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return false;
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}
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void vgpu_release_profiler_reservation(
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struct dbg_session_gk20a *dbg_s,
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struct dbg_profiler_object_data *prof_obj)
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{
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struct gk20a *g = dbg_s->g;
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dbg_s->has_profiler_reservation = false;
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prof_obj->has_reservation = false;
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if (prof_obj->ch == NULL)
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g->global_profiler_reservation_held = false;
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/* If new reservation count is zero, notify server */
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g->profiler_reservation_count--;
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if (g->profiler_reservation_count == 0)
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vgpu_sendrecv_prof_cmd(dbg_s, TEGRA_VGPU_PROF_RELEASE);
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}
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static int vgpu_sendrecv_perfbuf_cmd(struct gk20a *g, u64 offset, u32 size)
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{
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struct mm_gk20a *mm = &g->mm;
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struct vm_gk20a *vm = mm->perfbuf.vm;
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struct tegra_vgpu_cmd_msg msg;
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struct tegra_vgpu_perfbuf_mgt_params *p =
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&msg.params.perfbuf_management;
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int err;
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msg.cmd = TEGRA_VGPU_CMD_PERFBUF_MGT;
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msg.handle = vgpu_get_handle(g);
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p->vm_handle = vm->handle;
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p->offset = offset;
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p->size = size;
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err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
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err = err ? err : msg.ret;
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return err;
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}
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int vgpu_perfbuffer_enable(struct gk20a *g, u64 offset, u32 size)
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{
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return vgpu_sendrecv_perfbuf_cmd(g, offset, size);
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}
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int vgpu_perfbuffer_disable(struct gk20a *g)
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{
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return vgpu_sendrecv_perfbuf_cmd(g, 0, 0);
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}
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