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997ea5cef3
Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the xve sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Ieb9afc230199c341d2df1e9f75792a136a2a6067 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master/r/1510470 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
115 lines
3.2 KiB
C
115 lines
3.2 KiB
C
/*
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* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __XVE_GP106_H__
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#define __XVE_GP106_H__
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#include "gk20a/gk20a.h"
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#include <nvgpu/log2.h>
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int gp106_init_xve_ops(struct gpu_ops *gops);
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/*
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* Best guess for a reasonable timeout.
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*/
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#define GPU_XVE_TIMEOUT_MS 500
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/*
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* For the available speeds bitmap.
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*/
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#define GPU_XVE_SPEED_2P5 (1 << 0)
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#define GPU_XVE_SPEED_5P0 (1 << 1)
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#define GPU_XVE_SPEED_8P0 (1 << 2)
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#define GPU_XVE_NR_SPEEDS 3
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#define GPU_XVE_SPEED_MASK (GPU_XVE_SPEED_2P5 | \
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GPU_XVE_SPEED_5P0 | \
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GPU_XVE_SPEED_8P0)
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/*
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* The HW uses a 2 bit field where speed is defined by a number:
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*
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* NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED_2P5 = 1
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* NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED_5P0 = 2
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* NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED_8P0 = 3
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*
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* This isn't ideal for a bitmap with available speeds. So the external
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* APIs think about speeds as a bit in a bitmap and this function converts
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* from those bits to the actual HW speed setting.
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*
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* @speed_bit must have only 1 bit set and must be one of the 3 available
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* HW speeds. Not all chips support all speeds so use available_speeds() to
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* determine what a given chip supports.
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*/
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static inline u32 xve_speed_to_hw_speed_setting(u32 speed_bit)
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{
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if (!speed_bit ||
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!is_power_of_2(speed_bit) ||
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!(speed_bit & GPU_XVE_SPEED_MASK))
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return -EINVAL;
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return ilog2(speed_bit) + 1;
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}
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static inline const char *xve_speed_to_str(u32 speed)
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{
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if (!speed || !is_power_of_2(speed) ||
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!(speed & GPU_XVE_SPEED_MASK))
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return "Unknown ???";
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return speed & GPU_XVE_SPEED_2P5 ? "Gen1" :
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speed & GPU_XVE_SPEED_5P0 ? "Gen2" :
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speed & GPU_XVE_SPEED_8P0 ? "Gen3" :
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"Unknown ???";
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}
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/*
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* Debugging for the speed change.
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*/
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enum xv_speed_change_steps {
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PRE_CHANGE = 0,
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DISABLE_ASPM,
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DL_SAFE_MODE,
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CHECK_LINK,
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LINK_SETTINGS,
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EXEC_CHANGE,
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EXEC_VERIF,
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CLEANUP
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};
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#define xv_dbg(fmt, args...) \
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gk20a_dbg(gpu_dbg_xv, fmt, ##args)
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#define xv_sc_dbg(step, fmt, args...) \
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xv_dbg("[%d] %15s | " fmt, step, __stringify(step), ##args)
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void xve_xve_writel_gp106(struct gk20a *g, u32 reg, u32 val);
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u32 xve_xve_readl_gp106(struct gk20a *g, u32 reg);
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void xve_reset_gpu_gp106(struct gk20a *g);
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int xve_get_speed_gp106(struct gk20a *g, u32 *xve_link_speed);
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void xve_disable_aspm_gp106(struct gk20a *g);
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int xve_set_speed_gp106(struct gk20a *g, u32 next_link_speed);
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void xve_available_speeds_gp106(struct gk20a *g, u32 *speed_mask);
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int xve_sw_init_gp106(struct device *dev);
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#if defined(CONFIG_PCI_MSI)
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void xve_rearm_msi_gp106(struct gk20a *g);
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#endif
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void xve_enable_shadow_rom_gp106(struct gk20a *g);
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void xve_disable_shadow_rom_gp106(struct gk20a *g);
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#endif
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