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gpu: nvgpu: Reorg xve HAL initialization

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Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the xve
sub-module of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: Ieb9afc230199c341d2df1e9f75792a136a2a6067
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master/r/1510470
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Sunny He
2017-06-28 18:18:08 -07:00
committed by mobile promotions
parent 57abaabb76
commit 997ea5cef3
3 changed files with 41 additions and 36 deletions
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17
drivers/gpu/nvgpu/gp106/hal_gp106.c
View File

@@ -239,6 +239,21 @@ static const struct gpu_ops gp106_ops = {
.pg_gr_load_gating_prod =
gr_gp106_pg_gr_load_gating_prod,
},
.xve = {
.sw_init = xve_sw_init_gp106,
.get_speed = xve_get_speed_gp106,
.set_speed = xve_set_speed_gp106,
.available_speeds = xve_available_speeds_gp106,
.xve_readl = xve_xve_readl_gp106,
.xve_writel = xve_xve_writel_gp106,
.disable_aspm = xve_disable_aspm_gp106,
.reset_gpu = xve_reset_gpu_gp106,
#if defined(CONFIG_PCI_MSI)
.rearm_msi = xve_rearm_msi_gp106,
#endif
.enable_shadow_rom = xve_enable_shadow_rom_gp106,
.disable_shadow_rom = xve_disable_shadow_rom_gp106,
},
.get_litter_value = gp106_get_litter_value,
.chip_init_gpu_characteristics = gp106_init_gpu_characteristics,
.bios_init = gm206_bios_init,
@@ -253,6 +268,7 @@ int gp106_init_hal(struct gk20a *g)
gops->ltc = gp106_ops.ltc;
gops->clock_gating = gp106_ops.clock_gating;
gops->xve = gp106_ops.xve;
/* Lone functions */
gops->get_litter_value = gp106_ops.get_litter_value;
@@ -287,7 +303,6 @@ int gp106_init_hal(struct gk20a *g)
gk20a_init_css_ops(gops);
#endif
gp106_init_therm_ops(gops);
gp106_init_xve_ops(gops);
g->name = "gp10x";
gops->gr_ctx.use_dma_for_fw_bootstrap = true;

45
drivers/gpu/nvgpu/gp106/xve_gp106.c
View File

@@ -34,12 +34,12 @@
#define NV_PCFG 0x88000
static void xve_xve_writel_gp106(struct gk20a *g, u32 reg, u32 val)
void xve_xve_writel_gp106(struct gk20a *g, u32 reg, u32 val)
{
gk20a_writel(g, NV_PCFG + reg, val);
}
static u32 xve_xve_readl_gp106(struct gk20a *g, u32 reg)
u32 xve_xve_readl_gp106(struct gk20a *g, u32 reg)
{
return gk20a_readl(g, NV_PCFG + reg);
}
@@ -47,7 +47,7 @@ static u32 xve_xve_readl_gp106(struct gk20a *g, u32 reg)
/**
* Resets the GPU (except the XVE/XP).
*/
static void xve_reset_gpu_gp106(struct gk20a *g)
void xve_reset_gpu_gp106(struct gk20a *g)
{
u32 reset;
@@ -89,7 +89,7 @@ static void xve_reset_gpu_gp106(struct gk20a *g)
* bus speed is detected then *@xve_link_speed is not touched and -ENODEV is
* returned.
*/
static int xve_get_speed_gp106(struct gk20a *g, u32 *xve_link_speed)
int xve_get_speed_gp106(struct gk20a *g, u32 *xve_link_speed)
{
u32 status;
u32 link_speed, real_link_speed = 0;
@@ -161,7 +161,7 @@ static void set_xve_l1_mask(struct gk20a *g, int status)
/**
* Disable ASPM permanently.
*/
static void xve_disable_aspm_gp106(struct gk20a *g)
void xve_disable_aspm_gp106(struct gk20a *g)
{
u32 xve_priv;
@@ -450,7 +450,7 @@ done:
*
* If an error is encountered an appropriate error will be returned.
*/
static int xve_set_speed_gp106(struct gk20a *g, u32 next_link_speed)
int xve_set_speed_gp106(struct gk20a *g, u32 next_link_speed)
{
u32 current_link_speed;
int err;
@@ -472,7 +472,7 @@ static int xve_set_speed_gp106(struct gk20a *g, u32 next_link_speed)
/**
* Places a bitmask of available speeds for gp106 in @speed_mask.
*/
static void xve_available_speeds_gp106(struct gk20a *g, u32 *speed_mask)
void xve_available_speeds_gp106(struct gk20a *g, u32 *speed_mask)
{
*speed_mask = GPU_XVE_SPEED_2P5 | GPU_XVE_SPEED_5P0;
}
@@ -603,7 +603,7 @@ static const struct file_operations xve_link_control_status_fops = {
};
#endif
static int xve_sw_init_gp106(struct device *dev)
int xve_sw_init_gp106(struct device *dev)
{
int err = -ENODEV;
#ifdef CONFIG_DEBUG_FS
@@ -638,44 +638,21 @@ fail:
}
#if defined(CONFIG_PCI_MSI)
static void xve_rearm_msi_gp106(struct gk20a *g)
void xve_rearm_msi_gp106(struct gk20a *g)
{
/* We just need to write a dummy val in the CYA_2 offset */
g->ops.xve.xve_writel(g, xve_cya_2_r(), 0);
}
#endif
static void xve_enable_shadow_rom_gp106(struct gk20a *g)
void xve_enable_shadow_rom_gp106(struct gk20a *g)
{
g->ops.xve.xve_writel(g, xve_rom_ctrl_r(),
xve_rom_ctrl_rom_shadow_enabled_f());
}
static void xve_disable_shadow_rom_gp106(struct gk20a *g)
void xve_disable_shadow_rom_gp106(struct gk20a *g)
{
g->ops.xve.xve_writel(g, xve_rom_ctrl_r(),
xve_rom_ctrl_rom_shadow_disabled_f());
}
/*
* Init the HAL functions and what not. xve_sw_init_gp106() is for initializing
* all the other stuff like debugfs nodes, etc.
*/
int gp106_init_xve_ops(struct gpu_ops *gops)
{
gops->xve.sw_init = xve_sw_init_gp106;
gops->xve.get_speed = xve_get_speed_gp106;
gops->xve.set_speed = xve_set_speed_gp106;
gops->xve.available_speeds = xve_available_speeds_gp106;
gops->xve.xve_readl = xve_xve_readl_gp106;
gops->xve.xve_writel = xve_xve_writel_gp106;
gops->xve.disable_aspm = xve_disable_aspm_gp106;
gops->xve.reset_gpu = xve_reset_gpu_gp106;
#if defined(CONFIG_PCI_MSI)
gops->xve.rearm_msi = xve_rearm_msi_gp106;
#endif
gops->xve.enable_shadow_rom = xve_enable_shadow_rom_gp106;
gops->xve.disable_shadow_rom = xve_disable_shadow_rom_gp106;
return 0;
}

15
drivers/gpu/nvgpu/gp106/xve_gp106.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -97,5 +97,18 @@ enum xv_speed_change_steps {
#define xv_sc_dbg(step, fmt, args...) \
xv_dbg("[%d] %15s | " fmt, step, __stringify(step), ##args)
void xve_xve_writel_gp106(struct gk20a *g, u32 reg, u32 val);
u32 xve_xve_readl_gp106(struct gk20a *g, u32 reg);
void xve_reset_gpu_gp106(struct gk20a *g);
int xve_get_speed_gp106(struct gk20a *g, u32 *xve_link_speed);
void xve_disable_aspm_gp106(struct gk20a *g);
int xve_set_speed_gp106(struct gk20a *g, u32 next_link_speed);
void xve_available_speeds_gp106(struct gk20a *g, u32 *speed_mask);
int xve_sw_init_gp106(struct device *dev);
#if defined(CONFIG_PCI_MSI)
void xve_rearm_msi_gp106(struct gk20a *g);
#endif
void xve_enable_shadow_rom_gp106(struct gk20a *g);
void xve_disable_shadow_rom_gp106(struct gk20a *g);
#endif