Sagar Kamble f2ad7e0916 gpu: nvgpu: separate sec2 isr into common and hal ...

SEC2 isr handling requires message processing in common msg unit. That
unit requires interfaces from hal to know if the msg interrupt was
received, set the msg interrupt and handle other interrupts.

JIRA NVGPU-2025

Change-Id: I3b5ad8968ea9298cc769113417931c4678009cf1
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2085753
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2019-04-10 09:27:11 -07:00

..

nvgpu

gpu: nvgpu: separate sec2 isr into common and hal

2019-04-10 09:27:11 -07:00

Makefile

nvgpu: use kernel overlay features

2017-10-29 11:00:55 -07:00