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eb8db3e4df
Add below new APIs in common/linux/fuse.c and export them from include/nvgpu/fuse.h to read/write specific tegra fuse offsets void nvgpu_tegra_fuse_write_bypass(u32 val); void nvgpu_tegra_fuse_write_access_sw(u32 val); void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(u32 val); void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(u32 val); int nvgpu_tegra_fuse_read_gcplex_config_fuse(u32 *val); int nvgpu_tegra_fuse_read_reserved_calib(u32 *val); These APIs are needed to remove nvgpu's direct dependency on platform specific <soc/tegra/fuse.h> header Remove below generic APIs since they are no longer needed : nvgpu_tegra_fuse_read() nvgpu_tegra_fuse_write() Jira NVGPU-75 Change-Id: I366e6a3382f0c392b2132f4d3a7e286306bb2ec2 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1497517 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
56 lines
1.4 KiB
C
56 lines
1.4 KiB
C
/*
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <soc/tegra/fuse.h>
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#include <nvgpu/fuse.h>
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int nvgpu_tegra_get_gpu_speedo_id(void)
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{
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return tegra_sku_info.gpu_speedo_id;
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}
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/*
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* Use tegra_fuse_control_read/write() APIs for fuse offsets upto 0x100
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* Use tegra_fuse_readl/writel() APIs for fuse offsets above 0x100
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*/
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void nvgpu_tegra_fuse_write_bypass(u32 val)
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{
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tegra_fuse_control_write(val, FUSE_FUSEBYPASS_0);
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}
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void nvgpu_tegra_fuse_write_access_sw(u32 val)
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{
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tegra_fuse_control_write(val, FUSE_WRITE_ACCESS_SW_0);
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}
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void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(u32 val)
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{
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tegra_fuse_writel(val, FUSE_OPT_GPU_TPC0_DISABLE_0);
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}
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void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(u32 val)
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{
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tegra_fuse_writel(val, FUSE_OPT_GPU_TPC1_DISABLE_0);
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}
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int nvgpu_tegra_fuse_read_gcplex_config_fuse(u32 *val)
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{
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return tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, val);
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}
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int nvgpu_tegra_fuse_read_reserved_calib(u32 *val)
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{
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return tegra_fuse_readl(FUSE_RESERVED_CALIB0_0, val);
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}
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