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942029a433
Split handling of stalling interrupt to Linux specific chip agnostic and OS independent chip specific parts. Linux specific chip independent part contains handler for ISR and passing the control to a bottom half worker. It uses the new MC HALs intr_nonstall (query interrupt status), intr_nonstall_pause (pause interrupts), intr_nonstall_resume (resume interrupts), and is_intr1_pending (query per-engine interrupt bit). MC HAL isr_nonstall is removed, because its work is now handled in chip independent code. JIRA NVGPU-26 Change-Id: I3e4c9905ef6eef7f1cc9f71b0278518ae663f87e Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1497048 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
36 lines
1.4 KiB
C
36 lines
1.4 KiB
C
/*
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* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef MC_GK20A_H
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#define MC_GK20A_H
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struct gk20a;
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void gk20a_init_mc(struct gpu_ops *gops);
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void mc_gk20a_intr_enable(struct gk20a *g);
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void mc_gk20a_intr_unit_config(struct gk20a *g, bool enable,
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bool is_stalling, u32 mask);
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void mc_gk20a_isr_stall(struct gk20a *g);
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u32 mc_gk20a_intr_stall(struct gk20a *g);
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void mc_gk20a_intr_stall_pause(struct gk20a *g);
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void mc_gk20a_intr_stall_resume(struct gk20a *g);
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u32 mc_gk20a_intr_nonstall(struct gk20a *g);
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void mc_gk20a_intr_nonstall_pause(struct gk20a *g);
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void mc_gk20a_intr_nonstall_resume(struct gk20a *g);
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void gk20a_mc_enable(struct gk20a *g, u32 units);
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void gk20a_mc_disable(struct gk20a *g, u32 units);
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void gk20a_mc_reset(struct gk20a *g, u32 units);
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u32 gk20a_mc_boot_0(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev);
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bool mc_gk20a_is_intr1_pending(struct gk20a *g,
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enum nvgpu_unit unit, u32 mc_intr_1);
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#endif
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