mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-23 18:16:01 +03:00
Instead of using Linux APIs for mutex and spinlocks directly, use new APIs defined in <nvgpu/lock.h> Replace Linux specific mutex/spinlock declaration, init, lock, unlock APIs with new APIs e.g struct mutex is replaced by struct nvgpu_mutex and mutex_lock() is replaced by nvgpu_mutex_acquire() And also include <nvgpu/lock.h> instead of including <linux/mutex.h> and <linux/spinlock.h> Add explicit nvgpu/lock.h includes to below files to fix complilation failures. gk20a/platform_gk20a.h include/nvgpu/allocator.h Jira NVGPU-13 Change-Id: I81a05d21ecdbd90c2076a9f0aefd0e40b215bd33 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1293187 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
57 lines
1.5 KiB
C
57 lines
1.5 KiB
C
/*
|
|
* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms and conditions of the GNU General Public License,
|
|
* version 2, as published by the Free Software Foundation.
|
|
*
|
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
* more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
|
*/
|
|
#ifndef CLK_GP106_H
|
|
#define CLK_GP106_H
|
|
|
|
#include <nvgpu/lock.h>
|
|
|
|
#define CLK_NAMEMAP_INDEX_GPC2CLK 0x00
|
|
#define CLK_NAMEMAP_INDEX_XBAR2CLK 0x02
|
|
#define CLK_NAMEMAP_INDEX_SYS2CLK 0x07 /* SYSPLL */
|
|
#define CLK_NAMEMAP_INDEX_DRAMCLK 0x20 /* DRAMPLL */
|
|
|
|
#define CLK_DEFAULT_CNTRL_SETTLE_RETRIES 10
|
|
#define CLK_DEFAULT_CNTRL_SETTLE_USECS 5
|
|
|
|
#define XTAL_CNTR_CLKS 27000 /* 1000usec at 27KHz XTAL */
|
|
#define XTAL_CNTR_DELAY 1000 /* we need acuracy up to the ms */
|
|
#define XTAL_SCALE_TO_KHZ 1
|
|
|
|
|
|
|
|
struct namemap_cfg {
|
|
u32 namemap;
|
|
u32 is_enable; /* Namemap enabled */
|
|
u32 is_counter; /* Using cntr */
|
|
struct gk20a *g;
|
|
union {
|
|
struct {
|
|
u32 reg_ctrl_addr;
|
|
u32 reg_ctrl_idx;
|
|
u32 reg_cntr_addr;
|
|
} cntr;
|
|
struct {
|
|
/* Todo */
|
|
} pll;
|
|
};
|
|
u32 scale;
|
|
char name[24];
|
|
};
|
|
|
|
void gp106_init_clk_ops(struct gpu_ops *gops);
|
|
|
|
#endif /* CLK_GP106_H */
|