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651f970d1c
Adding support for handling of chip specific ECC memory errors JIRA: GPUT19X-112 Change-Id: I1c04ac1d5233c332b300540eade1b73527c46ff7 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1489020 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
42 lines
1.3 KiB
C
42 lines
1.3 KiB
C
/*
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* GP10B ECC
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*
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* Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef _NVGPU_ECC_GP10B_H_
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#define _NVGPU_ECC_GP10B_H_
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struct gk20a_ecc_stat;
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struct ecc_gr_t18x {
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struct gk20a_ecc_stat sm_lrf_single_err_count;
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struct gk20a_ecc_stat sm_lrf_double_err_count;
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struct gk20a_ecc_stat sm_shm_sec_count;
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struct gk20a_ecc_stat sm_shm_sed_count;
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struct gk20a_ecc_stat sm_shm_ded_count;
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struct gk20a_ecc_stat tex_total_sec_pipe0_count;
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struct gk20a_ecc_stat tex_total_ded_pipe0_count;
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struct gk20a_ecc_stat tex_unique_sec_pipe0_count;
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struct gk20a_ecc_stat tex_unique_ded_pipe0_count;
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struct gk20a_ecc_stat tex_total_sec_pipe1_count;
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struct gk20a_ecc_stat tex_total_ded_pipe1_count;
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struct gk20a_ecc_stat tex_unique_sec_pipe1_count;
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struct gk20a_ecc_stat tex_unique_ded_pipe1_count;
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struct gk20a_ecc_stat l2_sec_count;
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struct gk20a_ecc_stat l2_ded_count;
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};
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#endif
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