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git://nv-tegra.nvidia.com/linux-nvgpu.git
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39f3a8b89f
Added fifo configuration support for gp104 and gp106. These GPU chips have more number of channel fifo and runlist than gp10b. Added get_num_fifos and eng_runlist_base_size function pointer to find out the actual value from HW headers. JIRA DNVGPU-25 Change-Id: I2322a6354eaa2af2b2605f3e9eedebf9827c7dda Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1164653 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
38 lines
1.3 KiB
Makefile
38 lines
1.3 KiB
Makefile
nvgpu-t18x := ../../../../nvgpu-t18x/drivers/gpu/nvgpu
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nvgpu-y += \
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$(nvgpu-t18x)/gp10b/gr_gp10b.o \
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$(nvgpu-t18x)/gp10b/gr_ctx_gp10b.o \
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$(nvgpu-t18x)/gp10b/ce_gp10b.o \
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$(nvgpu-t18x)/gp10b/mc_gp10b.o \
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$(nvgpu-t18x)/gp10b/fifo_gp10b.o \
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$(nvgpu-t18x)/gp10b/ltc_gp10b.o \
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$(nvgpu-t18x)/gp10b/mm_gp10b.o \
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$(nvgpu-t18x)/gp10b/fb_gp10b.o \
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$(nvgpu-t18x)/gp10b/pmu_gp10b.o \
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$(nvgpu-t18x)/gp10b/hal_gp10b.o \
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$(nvgpu-t18x)/gp10b/rpfb_gp10b.o \
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$(nvgpu-t18x)/gp10b/gp10b_gating_reglist.o \
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$(nvgpu-t18x)/gp10b/regops_gp10b.o \
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$(nvgpu-t18x)/gp10b/cde_gp10b.o \
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$(nvgpu-t18x)/gp10b/therm_gp10b.o \
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$(nvgpu-t18x)/gp10b/fecs_trace_gp10b.o \
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$(nvgpu-t18x)/gp10b/gp10b_sysfs.o \
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$(nvgpu-t18x)/gp10b/gp10b.o \
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$(nvgpu-t18x)/gp106/hal_gp106.o \
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$(nvgpu-t18x)/gp106/mm_gp106.o \
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$(nvgpu-t18x)/gp106/pmu_gp106.o \
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$(nvgpu-t18x)/gp106/gr_gp106.o \
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$(nvgpu-t18x)/gp106/gr_ctx_gp106.o \
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$(nvgpu-t18x)/gp106/acr_gp106.o \
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$(nvgpu-t18x)/gp106/sec2_gp106.o \
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$(nvgpu-t18x)/gp106/fifo_gp106.o
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nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t18x)/gp10b/platform_gp10b_tegra.o
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nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \
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$(nvgpu-t18x)/vgpu/gp10b/vgpu_hal_gp10b.o \
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$(nvgpu-t18x)/vgpu/gp10b/vgpu_gr_gp10b.o \
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$(nvgpu-t18x)/vgpu/gp10b/vgpu_mm_gp10b.o \
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$(nvgpu-t18x)/vgpu/gp10b/vgpu_fifo_gp10b.o
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