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39f3a8b89f
Added fifo configuration support for gp104 and gp106. These GPU chips have more number of channel fifo and runlist than gp10b. Added get_num_fifos and eng_runlist_base_size function pointer to find out the actual value from HW headers. JIRA DNVGPU-25 Change-Id: I2322a6354eaa2af2b2605f3e9eedebf9827c7dda Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1164653 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
31 lines
944 B
C
31 lines
944 B
C
/*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include "gk20a/gk20a.h"
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#include "gp10b/fifo_gp10b.h"
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#include "fifo_gp106.h"
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#include "hw_ccsr_gp106.h"
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#include "hw_fifo_gp106.h"
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static u32 gp106_fifo_get_num_fifos(struct gk20a *g)
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{
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return ccsr_channel__size_1_v();
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}
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void gp106_init_fifo(struct gpu_ops *gops)
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{
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gp10b_init_fifo(gops);
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gops->fifo.get_num_fifos = gp106_fifo_get_num_fifos;
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gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v;
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}
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