mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-22 17:36:20 +03:00
While mapping the buffer, first check if buffer is in vidmem, and if yes convert allocation into base address And then walk through each chunk to decide the alignment Add new API gk20a_mm_get_align() which returns the alignment based on scatterlist and aperture, and use this API to get alignment during mapping Enable big page support for pci by unsetting disable_bigpage Jira DNVGPU-97 Change-Id: I358dc98fac8103fdf9d2bde758e61b363fea9ae9 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1207673 (cherry picked from commit d14d42290eed4aa7a2dd2be25e8e996917a58e82) Reviewed-on: http://git-master/r/1210959 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
347 lines
7.6 KiB
C
347 lines
7.6 KiB
C
/*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include <linux/pm_runtime.h>
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#include "pci.h"
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#include "gk20a/gk20a.h"
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#include "gk20a/platform_gk20a.h"
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#define PCI_INTERFACE_NAME "card-%s%%s"
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static int nvgpu_pci_tegra_probe(struct device *dev)
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{
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return 0;
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}
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static int nvgpu_pci_tegra_remove(struct device *dev)
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{
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return 0;
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}
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static bool nvgpu_pci_tegra_is_railgated(struct device *pdev)
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{
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return false;
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}
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static struct gk20a_platform nvgpu_pci_device = {
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/* ptimer src frequency in hz */
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.ptimer_src_freq = 31250000,
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.probe = nvgpu_pci_tegra_probe,
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.remove = nvgpu_pci_tegra_remove,
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/* power management configuration */
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.railgate_delay = 500,
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.can_railgate = false,
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.can_elpg = false,
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/* power management callbacks */
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.is_railgated = nvgpu_pci_tegra_is_railgated,
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.default_big_page_size = SZ_64K,
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.ch_wdt_timeout_ms = 7000,
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.has_ce = true,
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};
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static struct pci_device_id nvgpu_pci_table[] = {
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{
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
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.class = PCI_BASE_CLASS_DISPLAY << 16,
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.class_mask = 0xff << 16,
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},
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{}
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};
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static irqreturn_t nvgpu_pci_isr(int irq, void *dev_id)
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{
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struct gk20a *g = dev_id;
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irqreturn_t ret_stall;
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irqreturn_t ret_nonstall;
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ret_stall = g->ops.mc.isr_stall(g);
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ret_nonstall = g->ops.mc.isr_nonstall(g);
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return (ret_stall == IRQ_NONE && ret_nonstall == IRQ_NONE) ?
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IRQ_NONE : IRQ_WAKE_THREAD;
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}
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static irqreturn_t nvgpu_pci_intr_thread(int irq, void *dev_id)
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{
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struct gk20a *g = dev_id;
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g->ops.mc.isr_thread_stall(g);
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g->ops.mc.isr_thread_nonstall(g);
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return IRQ_HANDLED;
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}
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static int nvgpu_pci_init_support(struct pci_dev *pdev)
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{
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int err = 0;
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struct gk20a *g = get_gk20a(&pdev->dev);
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g->regs = ioremap(pci_resource_start(pdev, 0),
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pci_resource_len(pdev, 0));
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if (IS_ERR(g->regs)) {
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gk20a_err(dev_from_gk20a(g), "failed to remap gk20a registers");
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err = PTR_ERR(g->regs);
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goto fail;
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}
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g->bar1 = ioremap(pci_resource_start(pdev, 1),
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pci_resource_len(pdev, 1));
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if (IS_ERR(g->bar1)) {
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gk20a_err(dev_from_gk20a(g), "failed to remap gk20a bar1");
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err = PTR_ERR(g->bar1);
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goto fail;
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}
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g->regs_saved = g->regs;
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g->bar1_saved = g->bar1;
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mutex_init(&g->dbg_sessions_lock);
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mutex_init(&g->client_lock);
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mutex_init(&g->ch_wdt_lock);
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mutex_init(&g->poweroff_lock);
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g->remove_support = gk20a_remove_support;
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return 0;
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fail:
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gk20a_remove_support(&pdev->dev);
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return err;
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}
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static char *nvgpu_pci_devnode(struct device *dev, umode_t *mode)
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{
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*mode = S_IRUGO | S_IWUGO;
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return kasprintf(GFP_KERNEL, "nvgpu-pci/%s", dev_name(dev));
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}
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static struct class nvgpu_pci_class = {
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.owner = THIS_MODULE,
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.name = "nvidia-pci-gpu",
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.devnode = nvgpu_pci_devnode,
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};
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#ifdef CONFIG_PM
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static int nvgpu_pci_pm_runtime_resume(struct device *dev)
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{
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return gk20a_pm_finalize_poweron(dev);
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}
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static int nvgpu_pci_pm_runtime_suspend(struct device *dev)
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{
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return 0;
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}
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static const struct dev_pm_ops nvgpu_pci_pm_ops = {
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.runtime_resume = nvgpu_pci_pm_runtime_resume,
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.runtime_suspend = nvgpu_pci_pm_runtime_suspend,
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.resume = nvgpu_pci_pm_runtime_resume,
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.suspend = nvgpu_pci_pm_runtime_suspend,
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};
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#endif
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static int nvgpu_pci_pm_init(struct device *dev)
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{
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#ifdef CONFIG_PM
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struct gk20a_platform *platform = gk20a_get_platform(dev);
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if (!platform->can_railgate) {
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pm_runtime_disable(dev);
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} else {
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if (platform->railgate_delay)
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pm_runtime_set_autosuspend_delay(dev,
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platform->railgate_delay);
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/*
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* Runtime PM for PCI devices is disabled by default,
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* so we need to enable it first
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*/
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pm_runtime_use_autosuspend(dev);
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pm_runtime_put_noidle(dev);
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pm_runtime_allow(dev);
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}
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#endif
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return 0;
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}
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static int nvgpu_pci_probe(struct pci_dev *pdev,
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const struct pci_device_id *pent)
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{
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struct gk20a_platform *platform = &nvgpu_pci_device;
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struct gk20a *g;
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int err;
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char *nodefmt;
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pci_set_drvdata(pdev, platform);
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g = kzalloc(sizeof(struct gk20a), GFP_KERNEL);
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if (!g) {
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gk20a_err(&pdev->dev, "couldn't allocate gk20a support");
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return -ENOMEM;
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}
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init_waitqueue_head(&g->sw_irq_stall_last_handled_wq);
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init_waitqueue_head(&g->sw_irq_nonstall_last_handled_wq);
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platform->g = g;
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g->dev = &pdev->dev;
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err = pci_enable_device(pdev);
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if (err)
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return err;
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pci_set_master(pdev);
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g->irq_stall = pdev->irq;
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g->irq_nonstall = pdev->irq;
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if (g->irq_stall < 0)
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return -ENXIO;
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err = devm_request_threaded_irq(&pdev->dev,
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g->irq_stall,
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nvgpu_pci_isr,
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nvgpu_pci_intr_thread,
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IRQF_SHARED, "nvgpu", g);
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if (err) {
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gk20a_err(&pdev->dev,
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"failed to request irq @ %d", g->irq_stall);
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return err;
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}
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disable_irq(g->irq_stall);
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if (strchr(dev_name(&pdev->dev), '%')) {
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gk20a_err(&pdev->dev, "illegal character in device name");
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return -EINVAL;
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}
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nodefmt = kasprintf(GFP_KERNEL, PCI_INTERFACE_NAME, dev_name(&pdev->dev));
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if (!nodefmt)
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return -ENOMEM;
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err = gk20a_user_init(&pdev->dev, nodefmt, &nvgpu_pci_class);
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kfree(nodefmt);
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nodefmt = NULL;
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if (err)
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return err;
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err = nvgpu_pci_init_support(pdev);
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if (err)
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return err;
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init_rwsem(&g->busy_lock);
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mutex_init(&platform->railgate_lock);
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spin_lock_init(&g->mc_enable_lock);
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gk20a_debug_init(&pdev->dev);
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/* Initialize the platform interface. */
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err = platform->probe(&pdev->dev);
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if (err) {
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gk20a_err(&pdev->dev, "platform probe failed");
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return err;
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}
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/* Set DMA parameters to allow larger sgt lists */
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pdev->dev.dma_parms = &g->dma_parms;
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dma_set_max_seg_size(&pdev->dev, UINT_MAX);
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g->gr_idle_timeout_default =
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CONFIG_GK20A_DEFAULT_TIMEOUT;
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if (tegra_platform_is_silicon())
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g->timeouts_enabled = true;
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g->runlist_interleave = true;
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g->timeslice_low_priority_us = 1300;
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g->timeslice_medium_priority_us = 2600;
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g->timeslice_high_priority_us = 5200;
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gk20a_create_sysfs(&pdev->dev);
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g->mm.has_physical_mode = false;
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g->mm.vidmem_is_vidmem = true;
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#ifdef CONFIG_DEBUG_FS
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g->mm.ltc_enabled = true;
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g->mm.ltc_enabled_debug = true;
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#endif
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g->mm.bypass_smmu = platform->bypass_smmu;
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g->mm.disable_bigpage = platform->disable_bigpage;
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gk20a_init_gr(g);
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err = nvgpu_pci_pm_init(&pdev->dev);
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if (err) {
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gk20a_err(&pdev->dev, "pm init failed");
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return err;
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}
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return 0;
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}
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static void nvgpu_pci_remove(struct pci_dev *pdev)
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{
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struct gk20a_platform *platform = gk20a_get_platform(&pdev->dev);
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struct gk20a *g = get_gk20a(&pdev->dev);
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if (g->remove_support)
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g->remove_support(g->dev);
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gk20a_user_deinit(g->dev, &nvgpu_pci_class);
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debugfs_remove_recursive(platform->debugfs);
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debugfs_remove_recursive(platform->debugfs_alias);
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gk20a_remove_sysfs(g->dev);
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if (platform->remove)
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platform->remove(g->dev);
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kfree(g);
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}
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static struct pci_driver nvgpu_pci_driver = {
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.name = "nvgpu",
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.id_table = nvgpu_pci_table,
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.probe = nvgpu_pci_probe,
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.remove = nvgpu_pci_remove,
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#ifdef CONFIG_PM
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.driver.pm = &nvgpu_pci_pm_ops,
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#endif
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};
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int __init nvgpu_pci_init(void)
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{
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int ret;
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ret = class_register(&nvgpu_pci_class);
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if (ret)
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return ret;
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return pci_register_driver(&nvgpu_pci_driver);
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}
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void __exit nvgpu_pci_exit(void)
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{
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pci_unregister_driver(&nvgpu_pci_driver);
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class_unregister(&nvgpu_pci_class);
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}
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