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For ASIL-D decomposision we need hw register checker to validate potential register configurations done at init phase This is the tool used to generate hw registers table that needs to be validated on the target. * Generate register list - register addresses are picked from hw headers - register value masks are hardcoded for validation Jira NVGPU-8885 Change-Id: I875735b6ae6b5e94eb85e67ca802a23b7d250598 Signed-off-by: Sagar Kadamati <skadamati@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2823929 Reviewed-by: Alex Waterman <alexw@nvidia.com>
14 lines
462 B
Plaintext
14 lines
462 B
Plaintext
For ASIL-D decomposision we need hw register checker to validate
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potential register configurations done at init phase
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This is the tool used to generate hw registers table that needs to be
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validated on the target.
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* HW Register Table generator and instructions
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cd $TEGRA_TOP/kernel/nvgpu/scripts/checker/hw_register_generator
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make
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make generate
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* Generated hw table is located at
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$TEGRA_TOP/qnx/src/resmgrs/nvrm/nvgpu_rmos/checker/hw_registers_table.c
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